A STAFAN-like functional testability measure for register-level circuits

Ravikumar, C.P.; Saund, G.S.; Agrawal, Nitin

doi:10.1109/ats.1995.485336

Cited by 4 publications

(3 citation statements)

References 15 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…[1], [2], [4]- [7], [9], [11], [13]- [14], [20]. However, only a few papers that address the testability estimation at RTL [8], [12], [15], [17]- [19]. Logical Virtual Prototyping method [8], which utilizes a fast synthesis engine with a generic library is proposed recently.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A register-transfer level testability analyzer

Chen

Wang

Huang

et al. 2011

2011 IEEE International SOC Conference

View full text Add to dashboard Cite

This paper presents a statistic-based method to estimate the testability of a design at RegisterTransfer Level. This testability estimation technique is composed of a new proposed high-level design representation and a Monte Carlo simulation which exploits a statistic model to bound the error rate and confidence level of simulation results. The experimental results show that the proposed method can efficiently report more than 60% hard-to-test points of an RL design on average prior to the synthesis task.

show abstract

Section: Introductionmentioning

confidence: 99%

“…FSTAFAN [12] calculates fault detection probability by applying a well-known testability analysis algorithm, STAFAN [9]. It only uses the fault-free simulation to evaluate the testability, and hence gaining the benefit of efficiency over other testability analysis methods.…”

Section: Introductionmentioning

confidence: 99%

A register-transfer level testability analyzer

Chen

Wang

Huang

et al. 2011

2011 IEEE International SOC Conference

View full text Add to dashboard Cite

show abstract

“…Later, fault models were expanded to path delay faults and also sequential circuits [11][24] [6]. Some high-level testability measurements were also introduced [25] and an extension of STAFAN to RTL components was proposed [26]. Since most of the statistical methods use good simulation data, their run-time is comparable to the run-time of good simulation, which makes them scalable.…”

Section: Introductionmentioning

confidence: 99%

FALCON: Rapid statistical fault coverage estimation for complex designs

Mirkhani

Abraham

et al. 2012

2012 IEEE International Test Conference

View full text Add to dashboard Cite

Abstract-FALCON (FAst fauLt COverage estimatioN) is a scalable method for fault grading which uses local fault simulations to estimate the fault coverage of a large system. The generality of this method makes it applicable for any modular design. Our analysis shows that the run time of our algorithm is related to the number of gates and the number of IOs in a module, while fault simulation run time is related to the total number of gates in the system. We have measured fault coverage for OR1200 and IVM processors and compared the results with fault simulation performed by a commercial tool. We have also compared our results with fault sampling. Our results show that for large designs FALCON works faster (one order of magnitude) compared to fault simulation. It also has smaller error rate compared to fault sampling when the size of design under test grows.

show abstract

Designing self test programs for embedded DSP cores

Rizk¹,

Papachristou²,

Wolff³

Proceedings Design, Automation and Test in Europe Conference and Exhibition

View full text Add to dashboard Cite

A STAFAN-like functional testability measure for register-level circuits

Cited by 4 publications

References 15 publications

A register-transfer level testability analyzer

A register-transfer level testability analyzer

FALCON: Rapid statistical fault coverage estimation for complex designs

Designing self test programs for embedded DSP cores

Contact Info

Product

Resources

About