A spurious reduction technique for high-speed direct digital synthesizers

Kushner, Lawrence J.; Ainsworth, M.T.

doi:10.1109/freq.1996.560276

Cited by 12 publications

(2 citation statements)

References 13 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Direct digital synthesis (DDS) is another application demanding high speed DACs with good spurious performance [13]. Specifications of SNR, SFDR, and adjacent channel power ratio in a narrow bandwidth are becoming more important than static specifications such as integral nonlinearity (INL) and differential nonlinearity (DNL).…”

Section: State-of-the-art High-speed Dacsmentioning

confidence: 99%

Radio frequency digital-to-analog converter

Luschas¹,

Schreier

Lee

2004

IEEE J. Solid-State Circuits

114

View full text Add to dashboard Cite

Dynamic performance of high speed, high resolution digital-to-analog converters (DACs) is limited by distortion at the data switching instants. Inter-symbol interference (ISI), imperfect timing synchronization and clock jitter are all culprits. A DAC output current controlled by an oscillating waveform is proposed to mitigate the effects of the switching distortion. The oscillating waveform should be a multiple (k*fs) of the sampling frequency (fs), where k>1. The waveforms can be aligned so that the data switching occurs in the zero regions of the oscillating output. This makes the DAC insensitive to switch dynamics and jitter. The architecture has the additional benefit of mixing the DAC impulse response energy to a higher frequency. An image of a low IF input signal can therefore be output directly at a high IF or RF frequency for transmit communications applications. A narrowband sigma-delta DAC with eight unit elements is chosen to demonstrate the radio frequency digital-to-analog converter (RF DAC) concept. A sigma-delta architecture allows the current source transistors to be smaller since mismatch shaping is employed. Smaller current source transistors have a lower drain capacitance, allowing large high frequency output impedance to be achieved without an extra cascode transistor. Elimination of the cascode reduces transistor headroom requirements and allows the DAC to be built with a 1.8V supply. The RF DAC prototype is targeted to GSM transmit specifications and implemented in 0.1 8ptm CMOS technology. Measured single-tone SFDR is -75dBc, SNR is 52dB, and IMD3 is -70.8dBc over a 17.5MHz bandwidth centered at 942.5MHz. Measured SNR has the predicted dependence on the phase alignment of the data clock and oscillating pulse.

show abstract

Section: State-of-the-art High-speed Dacsmentioning

confidence: 99%

Radio frequency digital-to-analog converter

Luschas¹,

Schreier

Lee

2004

IEEE J. Solid-State Circuits

114

View full text Add to dashboard Cite

show abstract

“…Appling this method, one first samples and quantifies a period of the signal waveform to be generized, memorizes the obtained binary waveform data in a memory, and then reads it via hardware circuit in certain sequence, converts the data via digital-to-analog (DA) circuit, finally output the analog waveform through a filter. In this work, an arbitrary waveform generator (AWG) is designed based on the theory of direct digital synthesis (DDS) [1][2][3][4][5][6][7] and on the analysis of the performance of the output signal. The design uses a field programmable-gate-array (FPGA) [3] chip to utilize the AWG.…”

mentioning

confidence: 99%

A Method on Realizing Signal Generator for Arbitrary Waveform

Zhou

Gong

et al. 2013

AMM

View full text Add to dashboard Cite

The basic approach of generating arbitrary waveform is the digital synthesis method. Appling this method, one first samples and quantifies a period of the signal waveform to be generized, memorizes the obtained binary waveform data in a memory, and then reads it via hardware circuit in certain sequence, converts the data via digital-to-analog (DA) circuit, finally output the analog waveform through a filter. In this work, an arbitrary waveform generator (AWG) is designed based on the theory of direct digital synthesis (DDS)[1-7]and on the analysis of the performance of the output signal. The design uses a field programmable-gate-array (FPGA)[3]chip to utilize the AWG. The preset and display of the output frequency and phase are controlled by a micro computer unit (MCU). The artribary waveform data can be downloaded and updated from a communication interface. The AWG can produce a high-resolution arbitrary waveform. The dissertation focuses on hardware circuit design, which has been accomplished, including power supply module, MCU system, high-speed DA converter, and filter, etc. The experimental prototype of the AWG has been made and tested systemly.At the end of the dissertation, the measurement result of the system is given and its error is analyzed. It is shown the AWG can output a sine wave, a triangle wave, a sawteeth wave, or a square wave within the frequency range from 0.01Hz to 15MHz with the step of 10mHz, or output an arbitrary waveform within the range from 0.01Hz to 20kHz.

show abstract

High Precision Broadband Direct-Spread Signal Delay Control Based on Phase Controlled Waveform Hermite Interpolation

Xin

Mei

2017

China Satellite Navigation Conference (CSNC) 2017 Proceedings: Volume I

View full text Add to dashboard Cite

A spurious reduction technique for high-speed direct digital synthesizers

Cited by 12 publications

References 13 publications

Radio frequency digital-to-analog converter

Radio frequency digital-to-analog converter

A Method on Realizing Signal Generator for Arbitrary Waveform

High Precision Broadband Direct-Spread Signal Delay Control Based on Phase Controlled Waveform Hermite Interpolation

Contact Info

Product

Resources

About