A spurious-free delta-sigma DAC using rotated data weighted averaging

Radke, R. E.; Eshraghi, A.; Fiez, T.S.

doi:10.1109/cicc.1999.777257

Cited by 8 publications

(5 citation statements)

References 2 publications

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“…DWA has the problem of distortion due to cyclic selection. Various methods have been proposed in order to address this problem [10], [11]. DEM depends on OSR and hence become ineffective for very low values of the OSR, which are sometimes required in wide band data converters [5].…”

Section: Multi-bit Delta-sigma Adcmentioning

confidence: 99%

A Delta-Sigma ADC with Stochastic Quantization

Hirai

Yano

Matsuoka

2015

IPSJ Transactions on System LSI Design Methodology

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An application of the stochastic A/D conversion to multi-bit delta-sigma modulators is considered, and a novel correction technique for D/A converter (DAC) error is proposed. The stochastic A/D conversion can reduce the area of the quantizer and allows large mismatches. The proposed calibration technique corrects DAC errors using a programmable quantizer. The programmable quantizer has a non-linear characteristic that cancels DAC errors. Using this technique, we can decrease the influence of DAC errors without using conventional dynamic element matching. This A/D converter has a non-linear quantization characteristic, so output digital code must be corrected using a programmable encoder. This code correction and setting of the quantization levels are carried out based on calibration data obtained using genetic algorithm.

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Section: Multi-bit Delta-sigma Adcmentioning

confidence: 99%

A Delta-Sigma ADC with Stochastic Quantization

Hirai

Yano

Matsuoka

2015

IPSJ Transactions on System LSI Design Methodology

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“…This effectively smooth out the DAC INL, but the low frequency components remain which are the major contributor to the dominant spurs. It is much more effective to dynamically perturb the level of each error segment using DEM, which centers the average level of each error segment at zero [15], [16], [17], [18].…”

Section: Dac Nonlinearitymentioning

confidence: 99%

A 3.3-V 12b 50-MS/s A/D Converter in 0.6-µm CMOS with over 80-dB SFDR

Pan

Segami

Choi

et al. 2000

Analog Circuit Design

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This paper discusses the impact of SFDR specification on the design of AID converter (ADC) in CMOS technology and describes the implementation of a prototype optimized for wide band SFDR performance for use in modem wireless base stations. The 6b-7b two-stage pipelined ADC using bootstrapping to linearize the sampling switch of on-chip track-hold achieves over 80 dB SFDR for signal frequencies up to 75 MHz at 50 MS/s without the need for trimming, calibration and dithering. INL is 1.3LSB, DNL is 0.8LSB. The 6b and 7b sub-ADC's are made efficient with averaging and folding. In 0.61J.m CMOS, the 16mm 2 ADC dissipates 850mW from 3.3V supply.

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“…In (9), and are arbitrary constants because each DAC error is an arbitrary constant. Thus, by assumption, for any selection of the constants , and , there exist constants and , and a sequence with the given set of PSD properties such that (14) It follows from (12) that (15) for any selection of constants, . Since 14is satisfied for any selection of and , suppose for each , and…”

Section: Conditions For Mismatch Shapingmentioning

confidence: 99%

“…Most variants of the DWA DAC are designed to reduce, relative to the DWA DAC, the harmonic distortion in the DAC noise. Examples of such DWA variants are presented in [8], [13], and [14]. To successfully reduce harmonic distortion, each of these published first-order architectures requires that the multibit DAC input includes a random component-e.g., the quantization noise from a modulator.…”

Section: E Qualitative Comparisonsmentioning

confidence: 99%

Necessary and sufficient conditions for mismatch shaping in a general class of multibit dacs

Welz

Galton

2002

IEEE Trans. Circuits Syst. II

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Multibit digital-to-analog converters (DACs) are often constructed by combining several 1-bit DACs of equal or different weights in parallel. In such DACs, component mismatches give rise to signal dependent error that can be viewed as additive DAC noise. In some cases these DACs use dynamic element matching techniques to decorrelate the DAC mismatch noise from the input sequence and suppress its power in certain frequency bands. Such DACs are referred to as mismatch-shaping DACs and have been used widely as enabling components in state-of-the-art 16 data converters. Several different mismatch-shaping DAC topologies have been presented, but theoretical analyses have been scarce and no general unifying theory has been presented in the previously published literature. This paper presents such a unifying theory in the form of necessary and sufficient conditions for a multibit DAC to be a mismatch-shaping DAC and applies the conditions to evaluate the DAC noise generated by several of the previously published mismatch-shaping DACs and qualitatively compare their behavior. Index Terms-Analog-to-digital (A/D), data converters, 16, digital-to-analog (D/A), dynamic element matching, linearized digital-to-analog converters (DACs), mismatch shaping, 61, spectral shaping. I. INTRODUCTION M OST multibit digital-to-analog converters (DACs) consist of multiple 1-bit DACs. In each case, the digital input sequence is decomposed into multiple 1-bit sequences each of which drives a 1-bit DAC. Each 1-bit DAC generates one of two analog output levels depending upon whether its input bit is high or low. The outputs of the 1-bit DACs are summed to form the output of the multibit DAC. The primary differences among the various multibit DAC architectures reside in how the multibit input sequence is mapped to the multiple 1-bit DAC input sequences, and how the output levels of the 1-bit DACs are scaled relative to each other.

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A spurious-free delta-sigma DAC using rotated data weighted averaging

Cited by 8 publications

References 2 publications

A Delta-Sigma ADC with Stochastic Quantization

A Delta-Sigma ADC with Stochastic Quantization

A 3.3-V 12b 50-MS/s A/D Converter in 0.6-µm CMOS with over 80-dB SFDR

Necessary and sufficient conditions for mismatch shaping in a general class of multibit dacs

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