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This paper discusses the impact of SFDR specification on the design of AID converter (ADC) in CMOS technology and describes the implementation of a prototype optimized for wide band SFDR performance for use in modem wireless base stations. The 6b-7b two-stage pipelined ADC using bootstrapping to linearize the sampling switch of on-chip track-hold achieves over 80 dB SFDR for signal frequencies up to 75 MHz at 50 MS/s without the need for trimming, calibration and dithering. INL is 1.3LSB, DNL is 0.8LSB. The 6b and 7b sub-ADC's are made efficient with averaging and folding. In 0.61J.m CMOS, the 16mm 2 ADC dissipates 850mW from 3.3V supply.

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This paper presents the design of an analog-front-end (AFE) integrated into a DSP-based transceiver for both serial 10 Gbps KR-backplane and long-reach-multimode-fiber (LRM) applications. The receiver consists of a programmable gain amplifier (PGA) and a 6-bit 4-way time-interleaved ADC, which is digitally calibrated to compensate for the offset, gain and phase mismatches between the interleaved channels. With a 5 GHz input signal, the ADC achieves overall SNDR of 29 dB, while the measured SNDR of flash sub-ADC is 31.6 dB. The power efficiency FoM of the complete interleaved ADC is 1.4 pJ per conversion step. The PLL uses a calibrated LC-VCO and the TX features a full-rate 3-tap de-emphasis at the output. Inductively tuned buffers connected in tandem are employed to distribute the 10 GHz clock. Random and deterministic jitter measured at the TX output are 0.38 ps rms and 2.65 ps pp , respectively. Implemented in 65 nm CMOS technology, the AFE occupies an area of 3 mm 2 and consumes 500 mW from a 1 V supply. BER of less than 10 15 is measured over legacy backplanes with 26 dB loss at Nyquist and the measured transceiver optical sensitivity is less than 13 dBm for all four LRM stressors, exceeding both the KR and the LRM specifications.