A SPICE COMPATIBLE MODEL OF ON-WAFER COUPLED INTERCONNECTS FOR CMOS RFICs

Shi, Xiaomeng; Yeo, Kiat Seng; Lim, Wei Meng; Anh, Manh; Boon, Chirn Chye

doi:10.2528/pier10010608

Cited by 10 publications

(6 citation statements)

References 16 publications

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“…Hence, the circuit interpretation in Figure 5(a), as well as the analytical expressions in (20), (21) are still valid.…”

Section: Model Extensionmentioning

confidence: 75%

“…Target of the analysis is the development of a circuit model easy to be implemented and simulated in SPICE. Indeed, the development of prediction tools aimed at EMC-oriented simulation of wiring harnesses [16][17][18] and digital interconnects [19,20] in this specific simulation environment has recently gained increasing attention from the EMC and SI communities.…”

Section: Introductionmentioning

confidence: 99%

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Modeling of Imbalance in Differential Lines Targeted to Spice Simulation

Grassi

Wu²,

Yang³

et al. 2015

PIER B

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Abstract-In this paper, a SPICE model representative for the mode conversion occurring in differential lines affected by imbalance either of the line cross-section and the terminal networks is developed. The model is based on the assumption of weak imbalance and allows approximate prediction of modal quantities, through separate modeling of the contributions due to line and termination imbalance by controlled sources with (possibly) frequency dependent gain. The proposed SPICE model is used to perform worst-case prediction of undesired modal voltages induced at line terminals by mode conversion.

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“…Hence, the circuit interpretation in Figure 5(a), as well as the analytical expressions in (20), (21) are still valid.…”

Section: Model Extensionmentioning

confidence: 75%

Section: Introductionmentioning

confidence: 99%

Modeling of Imbalance in Differential Lines Targeted to Spice Simulation

Grassi

Wu²,

Yang³

et al. 2015

PIER B

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“…P 1 , P 2 , and P 3 are connected to the corresponding node Z in , source terminal of M 1 , and ground, respectively. As shown in the physical layout, the inductance of L 2 is higher than that of L 1 for the non-center-tapped inductor, since L 2 contributes the negative resistance in (5). A simplified model of the tapped inductor is shown in Fig.…”

Section: Q-enhanced Inductormentioning

confidence: 99%

“…Scalable and advanced CMOS technologies demonstrate low-cost, highintegration, and good-reliability potentials which make digital, analog, and radio-frequency (RF) circuitry in a single chip realistic [1][2][3][4][5]. However, significant losses of CMOS inductors resulting from its lowresistivity substrate limit their system applications and integrations at radio frequencies [6,7].…”

Section: Introductionmentioning

confidence: 99%

Design of Low-Loss and Highly-Selective Cmos Active Bandpass Filter at K-Band

Wang

Huang²

2012

PIER

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Abstract-In this paper, a second-order Chebyshev active bandpass filter (BPF) with three finite transmission zeros is presented. The filter utilizes a tapped-inductor feedback technique to compensate resistive losses of on-chip inductors, and a shunt-feedback inductor between input and output ports to achieve the transmission zeros. Moreover, one transmission zero is in the lower stopband, and two transmission zeros are in the upper stopband, thus improving the selectivity of the filter significantly. The filter is designed and fabricated in a standard 0.18-µm CMOS technology with a chip area of 0.57 mm × 0.65 mm including all testing pads. The circuit draws 6 mA from a 0.7-V supply voltage. Additionally, the filter achieves a 1.65-dB insertion loss and 13.2-dB return loss with a 17% 3-dB bandwidth at 23.5 GHz. The measured NF and input P 1 dB is 6.7 dB and −3.5 dBm. The rejection levels at the transmission zeros are greater than 15.2 dB. Finally, the large-signal characterizations are also investigated by the 1-dB compression point (P 1 dB ) of the filter.

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“…However, the existence of probe pads significantly affects the S parameter measurement of the DUT. The pad is sensitive to the substrate effects due to its large metal plate area and limits the performance of the devices or circuits using pads [1][2][3][21][22][23].…”

Section: Introductionmentioning

confidence: 99%

Ann-Based Pad Modeling Technique for Mosfet Devices

Li¹,

Li²,

Zhao³

2011

PIER

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Abstract-In this paper, an approach for the pad modeling of the test structure for Metal Oxide Semiconductor Field Effect Transistor (MOSFET) up to 40 GHz is presented. The approach is based on a combination of the conventional equivalent circuit model and artificial neural network (ANN). The pad capacitances and series resistors are directly obtained from EM (electromagnetic) simulation of the S parameters with different size of pad and operating frequency. The parasitic elements in the test structure can be modeled by using a sub artificial neural network (SANN). So the pad capacitances and series resistors can be regarded as functions of the dimensions of the pad structure and operating frequencies by using SANN. Good agreement between the ANN-based modeling and EM simulation results has been demonstrated. In order to remove the impact of the parasitic elements, the de-embedding procedure for MOSFET device using ANN-based pad model is also demonstrated.

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A SPICE COMPATIBLE MODEL OF ON-WAFER COUPLED INTERCONNECTS FOR CMOS RFICs

Cited by 10 publications

References 16 publications

Modeling of Imbalance in Differential Lines Targeted to Spice Simulation

Modeling of Imbalance in Differential Lines Targeted to Spice Simulation

Design of Low-Loss and Highly-Selective Cmos Active Bandpass Filter at K-Band

Ann-Based Pad Modeling Technique for Mosfet Devices

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