A software-supported methodology for designing high-performance 3D FPGA architectures

Siozios, Kostas; Sotiriadis, K.; Pavlidis, Vasilis F.; Soudris, Dimitrios

doi:10.1109/vlsisoc.2007.4402472

Cited by 12 publications

(7 citation statements)

References 8 publications

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“…Table II clearly indicates that the proposed 3D FPGA design can provide significant advantages over the corresponding 2D architecture by reducing the performance in DPP on average 26.32% (non-interlaced) 20.91% (h = 2), and 13.16% (h = 4), respectively. Also, Table III shows that on average 34.72% (noninterlaced), 44.56% (h = 2), and 50.78% (h = 4) ADP reductions can be obtained from the proposed 3D FPGA design comparing with the 2D FPGA architecture.…”

Section: Comparisonsmentioning

confidence: 99%

“…In other words, one of the drawbacks in designing a 3D FPGA is that it would require more silicon area for implementation. Thus, the selection of appropriate connectivity across the different layers of the 3D FPGA architecture is essential to ensure the high performance design [20]. This paper proposes an interlaced S 2D -boxes and S 3D -boxes placement approach to reach the high performance in DPP and ADP for 3D FPGA design applications.…”

Section: Interlaced S-boxes Placementmentioning

confidence: 99%

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Interlaced switch boxes placement for three‐dimensional FPGA architecture design

Hsu

Huang

Lee

2010

Circuit Theory & Apps

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SUMMARYThree-dimensional (3D) field programmable gate array (FPGA) has evoked significant interest in wirelength reduction for routing requirement. However, the complex design of the 3D switch boxes will limit the performance improvement and suffer from the area efficiency problems. This paper proposed a systematic graph model (SGM) for 3D switch boxes design to simplify the design process and reduce the storage memory for path programming. An interlaced 3D switch boxes and two-dimensional (2D) switch boxes placement topology is also presented in this paper to design the 3D FPGA architecture for area efficiency purpose. The 3D place and route tool and TSMC 0.18-m CMOS process parameters are used to support building the experimental flow for verification. Performance evaluation shows that about 50% storage memory reduction can be obtained by using the proposed SGM-based switch design approach. Additionally, compared with conventional architectures of 2D FPGA, the proposed scheme based on interlaced switch boxes placement approach can approximately achieve 20% delay-power product improvement and 43% area-delay product reduction.

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Section: Comparisonsmentioning

confidence: 99%

Section: Interlaced S-boxes Placementmentioning

confidence: 99%

Interlaced switch boxes placement for three‐dimensional FPGA architecture design

Hsu

Huang

Lee

2010

Circuit Theory & Apps

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“…The first of them affects devices, where each layer can be thought as a "functional layer" [11,12], while in the latter approach each of the layers is specialized (i.e. memory, switches, logic, etc) [13]. Even thought the proposed architecture affects a 3D FPGA, where all the layers have identical hardware resources (i.e.…”

Section: Introductionmentioning

confidence: 99%

Three dimensional FPGA architectures: A shift paradigm for energy-performance efficient DSP implementations

Siozios

Soudris

Economakos

2009

2009 16th International Conference on Digital Signal Processing

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Modern applications exhibit increased complexity which introduces extra constraints during implementation related to delay, power consumption and silicon area. This problem is even more important when we deal with Digital System Processor (DSP) kernels, as there are demands for even higher clock frequencies and logic densities, which cannot be satisfied with existing design technologies. Three-dimensional (3D) integration is an emerging technology that promises to alleviate problems related to performance improvement, but up to now this new design approach has not been sufficiently explored. In this paper we propose a novel 3D FPGA architecture able to implement efficiently DSP applications. The proposed architecture is software-supported by a methodology targeting to explore DSP enhanced 3D FPGA devices. During our study we quantify a number of design parameters, such as the selected number of layers, the proper bonding approach, the process technology for each layer, etc. Comparison results prove the efficiency (in terms of performance and power consumption) of the new design paradigm, as compared to existing commercial devices with similar hardware resources.

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“…The interconnection network of largescale reconfigurable architectures exhibits increased resistance (R) and capacitance (C) values. However, in the 3D approach, the circuits are split up into smaller parts and stacked appropriately alleviating such problems [1,4,5].…”

Section: Introductionmentioning

confidence: 99%

“…More specifically, the first one is responsible for the application partitioning to device layers, the second one deals with the placement of each layer and the routing procedure on the 3D-reconfigurable architectures (with full-custom interconnection fabric), while the last one performs the power/energy estimations of these devices. All of them are part of the new Design Framework, named 3D MEANDER [5,15].…”

Section: Introductionmentioning

confidence: 99%

Architecture-Level Exploration of Alternative Interconnection Schemes Targeting 3D FPGAs: A Software-Supported Methodology

Siozios

Bartzas

Soudris

2008

International Journal of Reconfigurable Computing

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In current reconfigurable architectures, the interconnection structures increasingly contribute more to the delay and power consumption. The demand for increased clock frequencies and logic density (smaller area footprint) makes the problem even more important. Three-dimensional (3D) architectures are able to alleviate this problem by accommodating a number of functional layers, each of which might be fabricated in different technology. However, the benefits of such integration technology have not been sufficiently explored yet. In this paper, we propose a software-supported methodology for exploring and evaluating alternative interconnection schemes for 3D FPGAs. In order to support the proposed methodology, three new CAD tools were developed (part of the 3D MEANDER Design Framework). During our exploration, we study the impact of vertical interconnection between functional layers in a number of design parameters. More specifically, the average gains in operation frequency, power consumption, and wirelength are 35%, 32%, and 13%, respectively, compared to existing 2D FPGAs with identical logic resources. Also, we achieve higher utilization ratio for the vertical interconnections compared to existing approaches by 8% for designing 3D FPGAs, leading to cheaper and more reliable devices.

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A software-supported methodology for designing high-performance 3D FPGA architectures

Cited by 12 publications

References 8 publications

Interlaced switch boxes placement for three‐dimensional FPGA architecture design

Interlaced switch boxes placement for three‐dimensional FPGA architecture design

Three dimensional FPGA architectures: A shift paradigm for energy-performance efficient DSP implementations

Architecture-Level Exploration of Alternative Interconnection Schemes Targeting 3D FPGAs: A Software-Supported Methodology

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