A Soft-Error-Tolerant SAR ADC with Dual-Capacitor Sample-and-Hold Control for Sensor Systems

Ro, Duckhoon; Um, Minseong; Lee, Hyung Min

doi:10.3390/s21144768

Cited by 5 publications

(2 citation statements)

References 18 publications

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“…Ultra-low power consumption is required in these systems for signal sensing and processing to provide a long battery life. An analog-to-digital converter (ADC) is a key component in the processing of sensor output [ 1 , 2 , 3 ] and wireless communication [ 4 , 5 ]. Among various ADCs, successive approximation register (SAR) ADC is suitable for achieving high energy efficiency with low power consumption [ 6 ].…”

Section: Introductionmentioning

confidence: 99%

An 11.8-fJ/Conversion-Step Noise Shaping SAR ADC with Embedded Passive Gain for Energy-Efficient IoT Sensors

Choi

Lee

2022

Sensors

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Herein, we present a noise shaping successive-approximation-register (SAR) analog-to-digital converter (ADC) with an embedded passive gain multiplication technique. The noise shaping moves the in-band quantization noise from the signal band to out-of-band for improved signal-to-noise ratio (SNR). The proposed approach tackles the drawback of the previous active noise shaping (increased power and extra noise) and passive noise shaping (limited noise suppression and signal loss). Both noise shaping and gain multiplication are realized on-chip in an energy-efficient manner without an opamp. This approach uses only capacitors and switches in the finite impulse response (FIR) and infinite impulse response (IIR) filters. A comparator suppressing kickback noise is presented to handle the tradeoff between noise suppression and the filter capacitor size. The energy-efficient merged-capacitor switching (MCS) technique is effectively combined with rail-to-rail swing comparator and thermometer-coded capacitor array, which reduces the settling error in the digital to analog converter (DAC). The process-induced mismatch effect in the capacitive DAC is investigated using a behavioral model of the ADC. Additionally, we propose dynamic element matching (DEM) for the thermometer-coded capacitor array. The ADC is fabricated using a 0.18 μm CMOS process in an area of 0.26 mm2. Consuming 4.1 μW, the ADC achieves a signal-to-noise and distortion ratio (SNDR) of 66.5 dB and a spurious-free dynamic range (SFDR) of 79.1 dB. The figure-of-merit (FoM) of the ADC is 11.8 fJ/conversion-step.

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Section: Introductionmentioning

confidence: 99%

An 11.8-fJ/Conversion-Step Noise Shaping SAR ADC with Embedded Passive Gain for Energy-Efficient IoT Sensors

Choi

Lee

2022

Sensors

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“…Developed for decades it has become fundamental and one of the most successful analog-to-digital conversion techniques. Nowadays, it is usually chosen as compromise between fast but expensive flash and precise but slow integrating analog-to-digital conversion method [1][2][3].…”

Section: Introductionmentioning

confidence: 99%

Systematization and Comparison of the Binary Successive Approximation Variants

Jurasz

Kościelnik

Szyduczyński

et al. 2021

Sensors

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This paper presents a systematization and a comparison of the binary successive approximation (SA) variants. Three different variants are distinguished and all of them are applied in the analog-to-digital conversion. Regardless of an analog-to-digital converter circuit solution, the adoption of the specific SA variant imposes a particular character of the conversion process and related parameters. One of them is the ability to direct conversion of non-removeable physical quantities such as time intervals. Referencing to this aspect a general systematization of the variants and a name for each of them is proposed. In addition, the article raises the issues related to the complexity of implementation and energy consumption for each of the discussed binary SA variants.

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Miniaturization for wearable EEG systems: recording hardware and data processing

2022

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As more people desire at-home diagnosis and treatment for their health improvement, healthcare devices have become more wearable, comfortable, and easy to use. In that sense, the miniaturization of electroencephalography (EEG) systems is a major challenge for developing daily-life healthcare devices. Recently, because of the intertwined relationship between EEG recording and processing, co-research of EEG recording hardware and data processing has been emphasized for whole-in-one miniaturized EEG systems. This paper introduces miniaturization techniques in analog-front-end hardware and processing algorithms for such EEG systems. To miniaturize EEG recording hardware, various types of compact electrodes and mm-sized integrated circuits (IC) techniques including artifact rejection are studied to record accurate EEG signals in a much smaller manner. Active electrode and in-ear EEG technologies are also researched to make small-form-factor EEG measurement structures. Furthermore, miniaturization techniques for EEG processing are discussed including channel selection techniques that reduce the number of required electrode channel and hardware implementation of processing algorithms that simplify the EEG processing stage.

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A Soft-Error-Tolerant SAR ADC with Dual-Capacitor Sample-and-Hold Control for Sensor Systems

Cited by 5 publications

References 18 publications

An 11.8-fJ/Conversion-Step Noise Shaping SAR ADC with Embedded Passive Gain for Energy-Efficient IoT Sensors

An 11.8-fJ/Conversion-Step Noise Shaping SAR ADC with Embedded Passive Gain for Energy-Efficient IoT Sensors

Systematization and Comparison of the Binary Successive Approximation Variants

Miniaturization for wearable EEG systems: recording hardware and data processing

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