A sinusoidal reference signal based high accuracy timing skew mismatch estimation scheme for time interleaved ADC

Xiao, Ruwu; Lei, Qiying; Guo, Xuan; Zhao, Yuping

doi:10.1109/iscit.2017.8261195

Cited by 2 publications

(2 citation statements)

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“…There are many researches on timing skew in recent two decades [2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30], along with numerous relevant calibration methods raised. Reference-signal-injection methods in [2,3,4,5] detect timing skew with a predetermined input signal, which are straightforward and effective.…”

Section: Introductionmentioning

confidence: 99%

“…But like all other foreground cali-bration methods, the calibration procedures cannot be performed without interrupting ADC's work. FIR filters can eliminate skew-related errors in parallel with normal system's operation [6,7,8,9,10,11,12], but this approach places certain restrictions on the bandwidth of input. What's worse, the increase of ADC's resolution rate will lead to an explosive boosting of the filters scale, which limited its application for high precision requirement.…”

Section: Introductionmentioning

confidence: 99%

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An efficient background timing skew calibration technique for time-interleaving analog-to-digital converters

Cao

Miao

et al. 2019

IEICE Electron. Express

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An efficient background timing skew calibration algorithm is proposed in this article, which detects the sampling time mismatches in time-interleaving analog-to digital converter (TIADC) by estimating the skew-related errors with a reference channel and aligns the sampling edge of each sub-ADC to that of the reference channel by analog variable-delay lines in the negative feedback loop. Compared with conventional background calibration methods based on complex algorithms or serious input restrictions, the proposed technique detects timing skews by only negligible hardware consisting of simple digital blocks and is applicable for a wide range of input including completely random signals. The detailed theoretical analysis and sufficient simulated results revealed that this algorithm is not sensitive to some non-ideal components in actual circuits like mismatches between channels or jitters in clock circuits, which verifies the practicability and robustness of this method.

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