An efficient background timing skew calibration technique for time-interleaving analog-to-digital converters

Cao, Yu; Miao, Peng Cheng; Li, Fēi; Wang, Huan

doi:10.1587/elex.16.20190352

Cited by 5 publications

(2 citation statements)

References 30 publications

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“…With the support of a complete modern digital signal processing theoretical system, it has become a trend to design background digital calibration algorithms to improve ADC performance [1][2][3] . It does not require changing the internal circuit structure of the ADC, but corrects errors in the digital domain by analyzing the digital code output by the ADC.…”

Section: Introductionmentioning

confidence: 99%

Research on an accuracy improvement technology of ADC acquisition system based on pruning neural network

Fang,

Zhang,

Zhou

2024

International Conference on Mechatronic Engineering and Artificial Intelligence (MEAI 2023)

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This paper introduces an algorithm for improving the accuracy of the ADC acquisition system based on pruning neural network, which can calibrate the errors caused by the analog-to-digital conversion module and other parts in the acquisition system, and effectively improve the accuracy of the ADC acquisition system. By using techniques such as neuron pruning, weight clustering, and parameter quantization, the network we trained greatly reduces hardware resource consumption while achieving the calibration effect of a fully connected neural network. It enables this network easier to deploy in embedded systems. The simulation results show that in the case of a signal input close to the Nyquist frequency, for a 12bit 12.5MS/s ADC acquisition system , the ENOB can be increased from 5.31 to 8.83, and the SFDR can be increased from 46.3dB to 66.4dB.

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Section: Introductionmentioning

confidence: 99%

Research on an accuracy improvement technology of ADC acquisition system based on pruning neural network

Fang,

Zhang,

Zhou

2024

International Conference on Mechatronic Engineering and Artificial Intelligence (MEAI 2023)

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show abstract

“…Moreover, compensation means in the analog domain are also feasible. The work of [31] employed digital-to-analog converters (DACs) and delay lines to compensate, nonetheless, the accuracy of this was obviously affected by the operating environment of the devices.…”

Section: Introductionmentioning

confidence: 99%

A Digital Timing-Mismatch Calibration Technique for Time-Interleaved ADCs Based on a Coordinate Rotational Digital Computer Algorithm

et al. 2023

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Timing-mismatch errors among channels in time-interleaved analog-to-digital converters (TIADCs) greatly degrade the whole performance of the system. Therefore, techniques for calibrating timing mismatch are indispensable, and a new fully-digital calibration technique is presented in this article. Based on a Hilbert filter, modified moving averagers (MMAs) and inverse cosine functions, the proposed estimation algorithm is fast (within 1200 sample points) and accurate. Meanwhile, the coordinate rotational digital computer (CORDIC) algorithm, which is used to implement inverse cosine functions, is also improved, giving it higher precision. In addition, a compensation method based on second-order Taylor series approximation with less hardware resource consumption is provided. Through analyses and simulations, this calibration technique proved to be suitable for TIADCs with an arbitrary number of channels, in which the signal-to-noise and distortion ratio (SNDR) and the spurious-free dynamic range (SFDR) were, respectively, improved from 24.06 dB and 24.57 dB to 67.96 dB and 85.69 dB.

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A field programmable gate array based high speed real-time weak periodic signal detection technique

Shen

Liu

et al. 2021

Review of Scientific Instruments

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The detection of a high repetition rate weak signal is studied in this paper. Owing to the characteristics of the signal of interest, both high speed analog-to-digital converter (ADC) and low computational complexity data processing techniques are required for high speed real-time weak signal detection. In this paper, a novel field programmable gate array (FPGA) based high speed real-time periodic weak signal detection technique is presented. Cascaded comparators outside the FPGA and cascaded flip flops in the FPGA are used to implement a one-bit ADC, which performs quantization first followed by sampling. Based on this novel design, a time-interleaved structure with several sub-channels is further proposed to significantly improve the sampling rate of the one-bit ADC, which does not require calibration for offset, gain, and sample-time mismatches between sub-channels. Each sub-channel has a long-time coherent integration structure to coherently integrate the sampled one-bit data. A full layer clearance mechanism that only operates on specific bits of the integrated sums is proposed to overcome the influence of a noise baseline drift on the weak signal detection. Compared with the traditional adaptive threshold, this mechanism has a significantly lower computational complexity. A prototype with three sub-channels performing 1.5 Gs/s sampling is implemented to verify the proposed technique. The results obtained confirm its high sampling rate and noise baseline drift tolerance in weak signal detection.

show abstract

An efficient background timing skew calibration technique for time-interleaving analog-to-digital converters

Cited by 5 publications

References 30 publications

Research on an accuracy improvement technology of ADC acquisition system based on pruning neural network

Research on an accuracy improvement technology of ADC acquisition system based on pruning neural network

A Digital Timing-Mismatch Calibration Technique for Time-Interleaved ADCs Based on a Coordinate Rotational Digital Computer Algorithm

A field programmable gate array based high speed real-time weak periodic signal detection technique

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