A Single-Slope Look-Ahead Ramp (SSLAR) ADC for Column Parallel CMOS Image Sensors

Nelson, Fan Z.; Alam, Mustafa N.; Ay, Suat U.

doi:10.1109/wmed.2009.4816152

Cited by 6 publications

(3 citation statements)

References 2 publications

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“…In order to address the speed issue for single slope ramp (SSR) ADC, a new ADC algorithm and topology called single-slope look-ahead ramp (SSLAR-ADC) ADC was reported [7]. Correspondingly, a programmable ramp generator with changeable code hopping was also introduced.…”

Section: Single-slope Look-ahead Ramp (Sslar) Adcmentioning

confidence: 99%

“…Simulation on both standard gray images and CIF videos were conducted. It was determined that, by setting proper threshold and jump step, the algorithm results in increased ADC speed; improving frame rate of the CMOS image sensor without greatly degrading image quality [7]. For a single input, conversion can be greatly improved by using SSLAR ADC when a proper step size is chosen.…”

Section: Single-slope Look-ahead Ramp (Sslar) Adcmentioning

confidence: 99%

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Integration of a New Column-Parallel ADC Technology on CMOS Image Sensor

Nelson

2010

2010 IEEE Workshop on Microelectronics and Electron Devices

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Abstract-A new analog-to-digital converter (ADC) technology called Single-slope look ahead ramp (SSLAR) analog-to-digital converter (ADC) was proposed for column-parallel CMOS image sensors. Additionally, a corresponding programmable ramp generator for SSLAR ADC was also designed in such a way that it only allows flexible code hopping (between 0 and 127 least significant bit (LSB)), code fall back and look-ahead operations in column-parallel ramp ADC. This new ADC technology is able to provide conversion speed improvement depending on individual image information with less than 1.0% image quality degradation. Simulation demonstrated that the conversion speed of this new ADC technology is 4-5x higher than a traditional single-slope ADC with minimal circuitry for processing 8-bit standard gray images as well as 3-4x for standard CIF videos. For processing higher resolution images, the conversion speed may further increase. A prototype chip using the 8-bit SSLAR ADC architecture was realized in a 0.5μm, 2P3M, CMOS process with a layout area of 8.2mm2 .

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Section: Single-slope Look-ahead Ramp (Sslar) Adcmentioning

confidence: 99%

Section: Single-slope Look-ahead Ramp (Sslar) Adcmentioning

confidence: 99%

Integration of a New Column-Parallel ADC Technology on CMOS Image Sensor

Nelson

2010

2010 IEEE Workshop on Microelectronics and Electron Devices

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“…All on-chip analogue or digital signal pro-cessing and conversion operations have to be optimised for lowpower and high-speed performance. Many algorithms were proposed to speed up these operations [2][3][4][5]. However, there is no objective image quality (IQ) metric to compare the effectiveness or quality of these algorithms proposed and used.…”

Section: Introductionmentioning

confidence: 99%

A new blind image conversion complexity metric for intelligent CMOS image sensors

Elmezayen

2020

IET Image Processing

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Many algorithms have been developed for complementary metal–oxide–semiconductor (CMOS) image sensors to speed up analogue‐to‐digital (A‐to‐D) conversion of captured images. However, there is no objective blind‐image quality metric available to compare and quantify the quality and effectiveness of these speed‐up algorithms. In this work, we developed a blind‐image quality and complexity metric for this purpose. The proposed metric relies on counting the successive zeros in a code histogram. The proposed metric is called the conversion complexity metric (CCM). The CCM is designed to quantify how complex, and to predict how much time and power consuming a captured image is for A‐to‐D conversion, mainly by integrating (ramp) type A‐to‐D converter used in column‐parallel architectures of a CMOS image sensor (CIS). The proposed metric, CCM, is tested for linearity, monotonicity, and sensitivity to many types of introduced distortion. The CCM is compared with other no‐reference and full‐reference image quality and complexity metrics. It accomplished, for brightness change distortion, 99% linearity and 316% sensitivity, providing a computationally efficient blind‐image quality metric that no other metrics provide for CIS to intelligently adjust and optimise on‐chip analogue and digital signal processing.

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An on-chip ramp generator for single-slope look ahead ramp (SSLAR) ADC

Balagopal

2009

2009 52nd IEEE International Midwest Symposium on Circuits and Systems

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A Single-Slope Look-Ahead Ramp (SSLAR) ADC for Column Parallel CMOS Image Sensors

Cited by 6 publications

References 2 publications

Integration of a New Column-Parallel ADC Technology on CMOS Image Sensor

Integration of a New Column-Parallel ADC Technology on CMOS Image Sensor

A new blind image conversion complexity metric for intelligent CMOS image sensors

An on-chip ramp generator for single-slope look ahead ramp (SSLAR) ADC

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