A single-event-hardened phase-locked loop using the radiation-hardened-by-design technique

Abstract

A radiation-hardened-by-design phase-locked loop (PLL) with a frequency range of 200 to 1000 MHz is proposed. By presenting a novel charge compensation circuit, composed by a lock detector circuit, two operational amplifiers, and four MOS devices, the proposed PLL significantly reduces the recovery time after the presence of a single event transient (SET). Comparing with many traditional hardened methods, most of which endeavor to enhance the immunity of the charge pump output node to an SET, the novel PLL can also decrease its susceptibility in the presence of an SET in other blocks. A novel system model is presented to describe immunity of a PLL to an SET and used to compare the sensitivity of traditional and hardened PLLs to an SET. An SET is simulated on Sentaurus TCAD simulation workbench to model the induced pulse current. Post simulation with a 130 nm CMOS process model shows that the recovery time of the proposed PLL reduces by up to 93.5% compared with the traditional one, at the same time, the charge compensation circuit adds no complexity to the systemic parameter design.

A Single-Event-Hardened Scheme of Phase-Locked Loop Microsystems for Aerospace Applications

“…It is often used to achieve frequency synthesis, clock generation, clock recovery, and other functions [18]. Figure 2 shows the topological structure of the charge pump phase-locked loop (CPPLL), which is mainly composed of five submodules, namely, the frequency discriminator (PFD), the charge pump (CP), the low-pass In recent years, in order to reduce the effect of the SET on a PLL, researchers have proposed various methods to reduce the SET sensitivity of the CP output stage [2,[13][14][15][16][17]. Loveless et al [15] proposed that the hardened scheme of changing the current-type CP to the voltage-type CP could effectively reduce the SET sensitivity.…”

“…This scheme effectively suppressed the SET effect of the CP; however, the introduction of a large resistance affected the dynamic characteristics of the PLL system and reduced the phase noise. Han et al [17] proposed a charge pump compensation structure consisting of a latch detection circuit, two operational amplifiers, and four MOS devices. They used the resistance in the low-pass filter (LPF) to detect the transient current and then used a charge-compensation circuit to compensate the charge to the LPF until the voltage on the LPF returned to the original value.…”

SET Detection and Compensation and Its Application in PLL Design

“…The DC characteristic curve can vary a lot if the input common mode voltage changes unless a more complex comparator structure is used, which will result in much more power consumption. Therefore, unlike [5] and [6], in order to preserve a reliable and consistent SET detection threshold the inputs of CMP P and CMP N are biased at 750 mV and are AC coupled to V CP . As a result, their input common mode voltage is fixed.…”

“…Moreover, the V-CP current dependency on the VCO control voltage leads to significant non-linearity as well as asymmetric charge and discharge current, which introduces static phase error. The third solution is to use a dedicated circuit to compensate the SET-induced charge [5,6]. SET is first detected and then a compensation circuit is used to remove the SET-induced charge.…”

“…Therefore, it imposes several constraints on PLL design. In [6], a low-speed operational amplifier (OpAmp) with its biasing scheme is proposed to shorten the PLL recovery time. However, the disturbance of the VCO control voltage is not effectively reduced due to the slow operation of the OpAmp.…”