A single-ended 12-bit 20 Msample/s self-calibrating pipeline A/D converter

Opris, I.E.; Lewicki, L.D.; Wong, B.C.

doi:10.1109/4.735529

Cited by 51 publications

(12 citation statements)

References 7 publications

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“…The gain error comes from capacitor mismatch, finite DC gain of the operational transconductance amplifier (OTA), the parasitic capacitor between the input and output nodes, and the incomplete settling. As a result, calibration [23], [24], [25], [26], [27], trimming, and error averaging [28], are necessary for resolution of 12b and above.…”

Section: A 15b/stagementioning

confidence: 99%

A 3.3-V 12b 50-MS/s A/D Converter in 0.6-µm CMOS with over 80-dB SFDR

Pan

Segami

Choi

et al. 2000

Analog Circuit Design

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This paper discusses the impact of SFDR specification on the design of AID converter (ADC) in CMOS technology and describes the implementation of a prototype optimized for wide band SFDR performance for use in modem wireless base stations. The 6b-7b two-stage pipelined ADC using bootstrapping to linearize the sampling switch of on-chip track-hold achieves over 80 dB SFDR for signal frequencies up to 75 MHz at 50 MS/s without the need for trimming, calibration and dithering. INL is 1.3LSB, DNL is 0.8LSB. The 6b and 7b sub-ADC's are made efficient with averaging and folding. In 0.61J.m CMOS, the 16mm 2 ADC dissipates 850mW from 3.3V supply.

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Section: A 15b/stagementioning

confidence: 99%

A 3.3-V 12b 50-MS/s A/D Converter in 0.6-µm CMOS with over 80-dB SFDR

Pan

Segami

Choi

et al. 2000

Analog Circuit Design

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“…Pipeline architecture has been found very suitable for calibration [81,83,65,84,85,79,86]. The number of components to be calibrated is sufficiently small, since only the errors in the first few stages are significant as a result of the fact that, when referred to the input, the errors in the latter stages are attenuated by the preceding gain.…”

Section: Calibrationmentioning

confidence: 99%

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Waltari¹,

Halonen²

2003

The International Series in Engineering and Computer Science

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The increasing digitalization in all spheres of electronics applications, from telecommunications systems to consumer electronics appliances, requires analog-to-digital converters (ADCs) with a higher sampling rate, higher resolution, and lower power consumption. The evolution of integrated circuit technologies partially helps in meeting these requirements by providing faster devices and allowing for the realization of more complex functions in a given silicon area, but simultaneously it brings new challenges, the most important of which is the decreasing supply voltage.Based on the switched capacitor (SC) technique, the pipelined architecture has most successfully exploited the features of CMOS technology in realizing high-speed high-resolution ADCs. An analysis of the effects of the supply voltage and technology scaling on SC circuits is carried out, and it shows that benefits can be expected at least for the next few technology generations. The operational amplifier is a central building block in SC circuits, and thus a comparison of the topologies and their low voltage capabilities is presented.It is well-known that the SC technique in its standard form is not suitable for very low supply voltages, mainly because of insufficient switch control voltage. Two low-voltage modifications are investigated: switch bootstrapping and the switched opamp (SO) technique. Improved circuit structures are proposed for both. Two ADC prototypes using the SO technique are presented, while bootstrapped switches are utilized in three other prototypes.An integral part of an ADC is the front-end sample-and-hold (S/H) circuit. At high signal frequencies its linearity is predominantly determined by the switches utilized. A review of S/H architectures is presented, and switch linearization by means of bootstrapping is studied and applied to two of the prototypes. Another important parameter is sampling clock jitter, which is analyzed and then minimized with carefully-designed clock generation and buffering.The throughput of ADCs can be increased by using parallelism. This is demonii strated on the circuit level with the double-sampling technique, which is applied to S/H circuits and a pipelined ADC. An analysis of nonidealities in double-sampling is presented. At the system level parallelism is utilized in a time-interleaved ADC. The mismatch of parallel signal paths produces errors, for the elimination of which a timing skew insensitive sampling circuit and a digital offset calibration are developed. A total of seven prototypes are presented: two double-sampled S/H circuits, a time-interleaved ADC, an IF-sampling self-calibrated pipelined ADC, a current steering DAC with a deglitcher, and two pipelined ADCs employing the SO technique.

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“…Recently, multi-pass ADCs (MP ADCs) with cyclic algorithmic forming of estimates of input signal on the basis of residual signal [9][10][11][12] have become one of the most intensively developing classes of low-energy ADCs. Iterative forming of estimates in the MP ADC gives the basis for application of optimal iterative algorithms for estimates calculation.…”

Section: Introductionmentioning

confidence: 99%