A Single-Controller-Four-Output Analog-Assisted Digital LDO with Adaptive-Time-Multiplexing Control in 65-nm CMOS

Lu, Yasu; Chen, Feng; Mok, Philip K. T.

doi:10.1109/esscirc.2019.8902511

Cited by 11 publications

(2 citation statements)

References 6 publications

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“…In addition, the compensation capacitor in the controller cannot be shared, making it difficult to expand to more output channels. A four-channel TDM digital LDO was presented in [6]. The controller is complicated, and the total chip area is larger than its analog counterpart.…”

Section: Monitor Kmentioning

confidence: 99%

A Four-Channel Gray-Code Addressing TDM Clocked-Analog LDO for Thermo-Optic Tuning in Silicon Photonics

ye¹,

Ye²,

Tan³

2021

Preprint

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This paper presents a Gray-code addressing time division multiplexing (TDM) clocked-analog low-dropout regulator (CLDO) that shares one controller between four output channels with only one compensation capacitor. We apply the Gray-code addressing strategy to reduce the crosstalk. We also apply the split-output amplifier structure to share the compensation capacitor for further chip area reduction. In addition, we introduce a lightweight local-generated supply to increase the dynamic range. Implemented in 130 nm CMOS process, this design has a total chip area of 0.056 mm2 , which is 67.5% smaller than the conventional solution with four identical LDOs. Post layout simulation results show that the presented four-channel TDM CLDO can simultaneously track four 1 Vpp sinusoidal signals at different frequencies with negligible crosstalk. This TDM CLDO is a promising solution for supplying multiple thermo-optic phase shifters (TOPSs) in silicon photonics

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Section: Monitor Kmentioning

confidence: 99%

A Four-Channel Gray-Code Addressing TDM Clocked-Analog LDO for Thermo-Optic Tuning in Silicon Photonics

ye¹,

Ye²,

Tan³

2021

Preprint

View full text Add to dashboard Cite

show abstract

“…A TDM multiple-output LDO (MO LDO) shares four power stages with two controllers but cannot handle multiple various outputs simultaneously [12]. TDM digital LDOs (TDM DL-DOs) share a controller between multiple power stages but they require complicated digital control circuits [13], [14]. The controller of TDM DLDOs occupies a large area, making these designs less satisfactory.…”

Section: Introductionmentioning

confidence: 99%

A Four-Channel TDM Clocked-Analog LDO Using a Shared Compensation Block for Thermo-Optic Tuning

Ye¹,

Xie²,

Ye³

et al. 2023

Preprint

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Time-division-multiplexing clocked-analog low dropout regulator (TDM CLDO) is a new multi-channel LDO architecture that is able to reduce the total chip area by analog hardware multiplexing. It is particularly suitable for thermo-optic tuning in silicon photonics that has a low tuning power and requires a small power supply chip area. However, previous designs require a dedicated compensation capacitor for each channel. This is because, during controller switching, one node of the compensation capacitor experiences large voltage changes that prevent reliable multiplexing of the capacitor. Multiplexing the compensation capacitor is required to further reduce chip area. This paper presents a four-channel TDM CLDO using a novel Current Miller compensation with a Degenerated Resistor (CMDR) block. This CDMR block is disconnected from voltage nodes with large changes, therefore enabling reliable capacitor multiplexing. In addition, Gray-code addressing technique is adopted to reduce the crosstalk between four channels caused by clock timing errors. Implemented in a 65 nm CMOS process, this design has a total chip area of 0.0047 mm2, which is 55% smaller than the conventional solution with four identical LDOs and consumes a quiescent current of 3.1 uA per channel. Measured results show that the presented four-channel TDM CLDO can simultaneously track four 1 Vpp sinusoidal signals up to 200 kHz.

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Architectural Advancement of Digital Low-Dropout Regulators

Akram

Hwang

2020

IEEE Access

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Digital Low-dropout (DLDO) regulators have been widely utilised for highly-efficient finegrained power delivery and management in system-on-chips (SoCs) due to their process scalability, ease of integration, and low-voltage operation. However, conventional DLDOs suffer gravely from the power-speed tradeoff, which arises from the use of sampling clocks. To obtain reasonable performance in the undershoot and recovery during load transient states, a large output capacitor is inevitably required in these DLDOs. Moreover, they inherently involve large steady-state voltage ripples and poor power-supply rejection (PSR). These limitations of synchronous DLDOs and their counter measures are thoroughly discussed in this paper. Various design strategies of major building blocks, i.e. comparators and power transistor arrays, are explained in detail with examples. Architectural advances are also expounded including state-of-the-art DLDO architectures such as clock-boosted synchronous, analog-assisted synchronous, asynchornous, eventdriven, and hybrid DLDOs. These state-of-the-art DLDOs do not only address the power-speed tradeoff and achieve fast load transient responses, but also can eliminate the use of an output capacitor in some cases. Moreover, some hybrid DLDOs successfully removed the steady state ripples and achieve high PSR. All of these DLDO are compared on basis of their performance metrics and figure-of-merits (FOMs).

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A Single-Controller-Four-Output Analog-Assisted Digital LDO with Adaptive-Time-Multiplexing Control in 65-nm CMOS

Cited by 11 publications

References 6 publications

A Four-Channel Gray-Code Addressing TDM Clocked-Analog LDO for Thermo-Optic Tuning in Silicon Photonics

A Four-Channel Gray-Code Addressing TDM Clocked-Analog LDO for Thermo-Optic Tuning in Silicon Photonics

A Four-Channel TDM Clocked-Analog LDO Using a Shared Compensation Block for Thermo-Optic Tuning

Architectural Advancement of Digital Low-Dropout Regulators

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