A single-chip adaptive DPCM video codec

Schobinger, M.; Zehner, B.; Matthiesen, F.; Totzek, U.; Hartl, J.; Reimann, Udo

doi:10.1109/4.34082

Cited by 3 publications

(1 citation statement)

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“…2~ CMOS technology. The feasibility of a single chip DPCM codec was first indicated in [6] and a VLSI implementation with an adaptive quantizer was presented in [7]. In this paper, we present the VLSI implementation of the pipelined ADPCM codec [4].…”

Section: Introductionmentioning

confidence: 99%

VLSI implementation of a 100 MHz pipelined ADPCM codec chip

Shanbhag

Parhi

Proceedings of IEEE Workshop on VLSI Signal Processing

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The VLSI implementation of a pipelined adaptive differential pulse-code modulation (ADPCM) video codec is described. The architecture for the ADPCM codec had been developed previously via the relaxed look-ahead technique. The result of this technique is a bit-parallel and bit-level pipelined architecture with minimal hardware overhead. All the arithmetic units employ redundant arithmetic for low-latency, carry-free computation. The pipelining latches are true single-phase and edge-triggered with a very compact structure. The pipelined ADPCM chip is designed in 1 . 2~ CMOS technology, with a total area of 5.6 x 8.8 mm2, an active area of 5.1 x 8.2 mm2 (136,000 transistors) and a projected speed of 100 MHz. This chip can be configured both as an encoder and a decoder. The codec has a compression ratio of 8 : 3 for a 256 x 256 image frame.

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Section: Introductionmentioning

confidence: 99%