VLSI implementation of a 100 MHz pipelined ADPCM codec chip

Abstract

The VLSI implementation of a pipelined adaptive differential pulse-code modulation (ADPCM) video codec is described. The architecture for the ADPCM codec had been developed previously via the relaxed look-ahead technique. The result of this technique is a bit-parallel and bit-level pipelined architecture with minimal hardware overhead. All the arithmetic units employ redundant arithmetic for low-latency, carry-free computation. The pipelining latches are true single-phase and edge-triggered with a very compact structure. The pipelined ADPCM chip is designed in 1 . 2~ CMOS technology, with a total area of 5.6 x 8.8 mm2, an active area of 5.1 x 8.2 mm2 (136,000 transistors) and a projected speed of 100 MHz. This chip can be configured both as an encoder and a decoder. The codec has a compression ratio of 8 : 3 for a 256 x 256 image frame.

Relaxed look-ahead pipelined LMS adaptive filters and their application to ADPCM coder

“…Both PIPLMS and PIPADPCM have a very low hardware overhead due to pipelining and are therefore attractive from a VLSI implementation point of view. Finite-precision properties of the PIPADPCM have been studied [34] and a VLSI chip has been successfully implemented [35].…”