A single chip 2.4 Gb/s CMOS optical receiver IC with low substrate crosstalk preamplifier

A CMOS optical preamplifier for wireless infrared communications

“…1(b). Level detection based on the peaks of the signal is effective [10], [11], but assumes that the average current is constant and requires a reset mechanism.…”

A 3-V CMOS optical preamplifier with DC photocurrent rejection

“…A feedback loop which includes an error amplifier is used to determine the optimum current level. Similar structures using peak-level detection have been reported [7][8]. However, by modifying the feedback loop to use simple low pass filtering instead of peak detection, the reset and control circuitry --possible sources of digital noise --are eliminated.…”

“…As well, the low frequency cut-off point, , is given by the unity loop-gain frequency. The open-loop gain, L(s), is given by (8) where is the frequency response of the error amplifier, and constant, , is determined by the geometry of Mctl and the CMOS process parameters. Because the bandwidth of this feedback loop is low, the frequency response of the error amplifier can be modeled using a single-pole response of (9) where is the dominant-pole frequency and Ao is the dc gain.…”

A 1V 4.2mW fully integrated 2.5Gb/s CMOS limiting amplifier using folded active inductors

“…Currently, commercial 2.5Gb/s SONET/STM systems are composed of several discrete chips, which are implemented in different processes such as GaAs, Si Bipolar and CMOS processes. However, with significant advancement in CMOS technology, various CMOS Gigabit receiver circuits have been demonstrated in many papers [1][2][3][4][5].…”

“…A typical gain gain stage is composed of an NMOS differential pair and PMOS loads. The LA which consists of the typical gain stages can operate up to 1.25Gb/s without any bandwidth enhancement technique [2]. However, to design a 2.5Gb/s LA, the performance of the typical gain stage is insufficient and the bandwidth enhancement, such as inductive shun peaking, is required.…”