A single-chip 2.4-Gb/s CMOS optical receiver IC with low substrate cross-talk preamplifier

Tanabe, A.; Soda, M.; Nakahara, Y.; Furukawa, Akira; Tamura, T.

doi:10.1109/4.735558

Cited by 35 publications

(5 citation statements)

References 6 publications

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“…3c show the SNR of the TTM and the TMLCM at a bit rate of 2.5 Gbps, a wide band PIN-FET optical receiver was considered for the SNR calculations [34]. The results show the significant improvement in the SNR under the TMLCM when compared with the TTM.…”

Section: Snr Analysismentioning

confidence: 84%

Transmitters mapping of visible light communication system

Al‐Hameed

Hussein

Alresheedi

et al. 2017

2017 19th International Conference on Transparent Optical Networks (ICTON)

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Section: Snr Analysismentioning

confidence: 84%

Transmitters mapping of visible light communication system

Al‐Hameed

Hussein

Alresheedi

et al. 2017

2017 19th International Conference on Transparent Optical Networks (ICTON)

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“…In the past years, the research activity has been focused on intra-chip communication using carefully-engineered [6]0 [8]. However, these techniques typically require peak hold circuits which determine a certain time for the system to settle, causing therefore loss of data, an undesirable event in optical networking applications.…”

Section: Introductionmentioning

confidence: 99%

2.6 GHz receiver for on-chip optical networking in 65nm CMOS technology

Fragomeni

Agostino

Scandurra

et al. 2010

2010 17th IEEE International Conference on Electronics, Circuits and Systems

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This paper presents a 2.6 GHz optical receiver with full rail to-rail output swing, designed in the ST 65 nm CMOS technology for the hybrid integration with a III-IV photodetector. The receiver consists of a 1 kn transimpedance amplifier (TIA) followed by a postamplifier based on a biased common source chain. The bias circuits allow for improving the robustness of the system against supply voltage fluctuations and temperature variations. The receiver has a simulated resolution of 2 llApp at 4 Gb/s, with an input capacitance of 0.1 pF, and draws approximately 2.6 mW from the 1 V supply. An instantaneous response multiple decision thresholds output stage is also proposed for overcoming the limitation of an automatic offset control circuie.Index Terms-Optical receiver, CMOS analog integrated circuits, optical interconnections, automatic offset control.

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“…However, the CMOS signal is much more sensitive than LVDS. In [3], the design methodology to reduce digital-to-analog substrate cross-talk noise is discussed. The phase-lock loop, 1:8 demultiplexer and AGC are used.…”

Section: Introductionmentioning

confidence: 99%

An Integrated Optical Sensor Receiver with the Sensitivity of 0.7 μA Fabricated with Standard CMOS Process

Liu

Huang

2012

AMM

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A fully integrated CMOS receiver front-end with digital output for optical signal processing system is presented. This circuit is composed of trans-impedance amplifier (TIA) for weak optical current detection, post-amplifier for both a linear and limiting amplification, control circuits and the digital output interface. Measured with photodiode which is driven by pulse voltage source, a sensitivity of 0.7μA was achieved. The current model methodology is employed to optimize the noise performance. The front-end consumes the current of 1.5mA with the power supply of 3.3V. The design was done in a low-cost standard CMOS process with 0.6μm featured size, taking area of 600μm×150μm excluding the bonding pads.

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A single-chip 2.4-Gb/s CMOS optical receiver IC with low substrate cross-talk preamplifier

Cited by 35 publications

References 6 publications

Transmitters mapping of visible light communication system

Transmitters mapping of visible light communication system

2.6 GHz receiver for on-chip optical networking in 65nm CMOS technology

An Integrated Optical Sensor Receiver with the Sensitivity of 0.7 μA Fabricated with Standard CMOS Process

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