A Single Chip 1024 Bits RSA Processor

Abstract

A new carry-free division algorithm will be described; it is based on the properties of RSD arithmetic to avoid carry propagation and uses the minimum hardware per bit i.e. one full-adder. Its application to a 1024 bits RSA cryptographic chip will be presented. Thanks to the features of this new algorithm, high performance (8 kbits/s for 1024 bits words) was obtained for relatively small area and power consumption (80 mm2 in a 2 pm CMOS process and 500 mW at 25 MHz).

Hardware architectures for public key cryptography

“…Vandemeulebroecke et al [195] presented a single chip 1 024-bit RSA processor in 1989. They used Redundant Signed Digit (RSD) arithmetic in an RSA computation for the first time.…”

Applied cryptography: Protocols, algorithms, and source code in C

“…Good survey articles are [258,872]. Many different chips perform RSA encryption [1310,252,1101,1317,874,69,737,594,1275,1563,509,1223]. A partial list of currently available RSA chips, from [150,258], is listed in Table 19.3.…”

A design of a fast pipelined modular multiplier based on a diminished-radix algorithm

“…An implementation with redundant-signed-digit arithmetic by Vandemeulebroecke et al [32] has an estimated throughput of 16 kbit/s for 512-bit encryption at 25 MHz. A2 #m CMOS chip was fabricated by UCL with 180,000 transistors (final test results were not published).…”

“…There are many variations on this theme [1], [7], [19], [22], [32], however, the number of bits that can be reduced in parallel is limited because the number of stored multiples of the modulus grows exponentially with the number of bits being reduced. There are many variations on this theme [1], [7], [19], [22], [32], however, the number of bits that can be reduced in parallel is limited because the number of stored multiples of the modulus grows exponentially with the number of bits being reduced.…”