A design of a fast pipelined modular multiplier based on a diminished-radix algorithm

Orton, G.A.; Peppard, L.; Tavares, Stafford E.

doi:10.1007/bf00203816

Cited by 4 publications

(3 citation statements)

References 22 publications

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“…Hence, the efficiency of the optimisation techniques is highest for computations with large operands. Orton, Peppard and Tavares [OPT93] have optimised a traditional high radix modular multiplication method using techniques very similar to the techniques described in this chapter. They utilise an adjustment of the modulus and a pipelined hardware architecture to obtain a recursion cycle time that is identical to the time for the optimised Montgomery method.…”

Section: Summary and Discussionmentioning

confidence: 99%

“…The fastest implementation of RSA cryptography is achieved by constructing dedicated hardware circuits. TY92,IMI92a,IMI92b,Sau92,EW93,Kor93b,OPT93,Wal93,Zha93,Kor94b,Oru95] In contrast to methods aimed for standard micro-processors, the methods of this thesis are not constrained by a standard architecture. Indeed, the additional freedom of specifying special-purpose hardware architectures is utilised to obtain optimal solutions where the hardware architecture are developed in harmony with the computation method.…”

Section: Chosen Approachmentioning

confidence: 99%

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Exponentiation, Modular Multiplication and VLSI Implementation of High-Speed RSA Cryptography

Orup¹

1995

DPB

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ProblemstillingAfhandlingen er motiveret af en problemstilling, der isaer er kendt fra anvendelsen af RSA kryptosystemet: Den praktiske anvendelighed af systemet er afhaengig af hastigheden, hvormed man er i stand til at udføre de tilhørende transformationer af data. For at undgå at anvendelsen af kryptografi bliver en flaskehals i de elektroniske kommunikationssystemer, er det vigtigt at opnå en tilstraekkelig høj transformationshastighed.Transformationerne, der benyttes i RSA kryptosystemet, er baseret på en aritmetisk operation på formen M e mod m kaldet modulo eksponentiering. Da operandernes størrelse typisk er på 500 bit eller mere, er modulo eksponentiering en forholdsvis tidskraevende operation. I 1990, da projektet startede, var den hurtigste implementering af modulo eksponentiering i stand til at foretage beregningerne med en hastighed på 29 Kbit/sek ved en operandstørrelse på 512 bit. i ii FormålHovedformålet med arbejdet praesenteret i afhandlingen er at undersøge mulighederne for at forøge hastigheden af modulo eksponentiering ved hjaelp af specialdesignede VLSI (Very Large Scale Integrated) kredsløb. Den konkrete målsaetning for projektet udført ved Tele Danmark/Jydsk Telefon var at konstruere et VLSI kredsløb, som kunne foretage module eksponentiering af operander på 561 bit med en hastighed på minimum 64 Kbit/sek. Endvidere skulle kredsløbet implementeres på en enkelt chip.Formålet med selve afhandlingen er at beskrive resultaterne opnået under studiet og at saette disse i perspektiv ved en diskussion og sammenligning med resultater kendt fra litteraturen. Desuden er det hensigten at give laeseren indsigt i de teknikker, der kan anvendes til at effektivisere modulo exponentiering. TilgangsvinkelDen valgte tilgangsvinkel er baseret pa en simpel analyse af VLSI implementeringer, der var kendt i 1990: Alle de hurtigste implementeringer bruger det samme antal klokke perioder til at foretage en modulo eksponentiering, og forskellen i hastighed kan tilsyneladende alene tilskrives forskellen i den anvendte klokkefrekvens. Dette kunne tyde på, at fremskridt i hastighed alene er nået på baggrund af hurtigere kredslebsteknologier, og ikke på grund af forbedrede beregningsmetoder. Derfor blev det besluttet at undersøge mulighederne for at udvikle nye og mere effektive beregningsmetoder, som er velegnede til VLSI implementering. Afhandlingens strukturAfhandlingen er opdelt i to separate dele. Den sidste del består af fire artikler, gengivet i appendices A-D, samt en rapport med beskrivelser af RSA kredsen i appendix E. Alle dokumenterne er skrevet i perioden fra 1990 til 1995. Artiklerne praesenterer nogle af de opnåede resultater. Den første del af afhandlingen indeholder en relativt udtømmende oversigt over relevante resultater fra litteraturen. Disse resultater diskuteres og sammenholdes med iii resultaterne opnået under studiet. Desuden er projektet med konstruktion af RSA kredsen beskrevet. OversigtsdelenDe første fire kapitler udgør en hierakisk struktureret fremstilling, hvor problemstillingerne ident...

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Section: Summary and Discussionmentioning

confidence: 99%

Section: Chosen Approachmentioning

confidence: 99%

Exponentiation, Modular Multiplication and VLSI Implementation of High-Speed RSA Cryptography

Orup¹

1995

DPB

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“…DR moduli are attractive for implementing the RSA (see, e.g., [21,24,34]) because they greatly simplify the modular reductions, which can be computed with only shifts, additions and single-precision multiplications. RSA moduli N can also be constructed under a sparse form, that is, with a reduced Hamming weight.…”

Section: Introductionmentioning

confidence: 99%

RSA Moduli with a Predetermined Portion: Techniques and Applications

Joye

Information Security Practice and Experience

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Abstract. This paper discusses methods for generating RSA moduli with a predetermined portion. Predetermining a portion enables to represent RSA moduli in a compressed way, which gives rise to reduced transmission-and storage requirements. The first method described in this paper achieves the compression rate of known methods but is fully compatible with the fastest prime generation algorithms available on constrained devices. This is useful for devising a key escrow mechanism when RSA keys are generated on-board by tamper-resistant devices like smart cards. The second method in this paper is a compression technique yielding a compression rate of about 2/3 instead of 1/2. This results in higher savings in both transmission and storage of RSA moduli. In a typical application, a 2048-bit RSA modulus can fit on only 86 bytes (instead of 256 bytes for the regular representation). Of independent interest, the methods for prescribing bits in RSA moduli can be used to reduce the computational burden in a variety of cryptosystems.

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On Quisquater’s Multiplication Algorithm

Joye

2012

Cryptography and Security: From Theory to Applications

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A design of a fast pipelined modular multiplier based on a diminished-radix algorithm

Cited by 4 publications

References 22 publications

Exponentiation, Modular Multiplication and VLSI Implementation of High-Speed RSA Cryptography

Exponentiation, Modular Multiplication and VLSI Implementation of High-Speed RSA Cryptography

RSA Moduli with a Predetermined Portion: Techniques and Applications

On Quisquater’s Multiplication Algorithm

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