A Simulation Study of NBTI Impact on 14-nm Node FinFET Technology for Logic Applications: Device Degradation to Circuit-Level Interaction

Mishra, Subrat; Amrouch, Hussam; Joe, Jerin; Dabhi, Chetan Kumar; Thakor, Karansingh; Chauhan, Yogesh Singh; Henkel, Jörg; Mahapatra, S.

doi:10.1109/ted.2018.2875813

Cited by 52 publications

(13 citation statements)

References 24 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Citation information: DOI 10.1109/JEDS.2020.3022180, IEEE Journal of the Electron Devices Society within the TCAD modeling. The interface traps are uniformly distributed across the entire energy bandgap as proposed in [17]. We consider the End-of-Lifetime (EOL) of a transistor to be when ∆V T reaches 50mV.…”

Section: Impact Of Interface Traps On Nc-pfinfetmentioning

confidence: 99%

“…The calibrations for the BSIM-CMG model are done to reproduce TCAD data for both nFinFET and pFinFET devices, similar to [7]. Note that our TCAD devices were also first calibrated to the 14 nm measurement data, as described earlier in Section 1 (only p-FinFET calibration was shown).…”

Section: Impact Of Interface Traps On Circuitsmentioning

confidence: 99%

“…In order to capture the effects of different ∆N it on V T , the corresponding BSIM-CMG parameter (DVTSHIFT) is accordingly modified. Similar to [7], the impact of SS degradation is empirically modeled in BSIM-CMG, through tuning the BSIM-CMG parameter (CIT) that represents the interface state capacitance, in order to capture the relation between ∆V T and ∆SS (see Fig. 7(a) and (b)).…”

Section: A Impact Of Interface Traps On Ring Oscillator Performancementioning

confidence: 99%

“…Negative Bias Temperature Instability (NBTI) is one of the major reliability concerns in current technology nodes, especially for p-type devices [5], [6]. NBTI-induced defects degrade the I ON of transistors due to its impact on increasing the threshold voltage (V T ) and degrading the sub-threshold slope (SS) [7]. Among different defect generation mechanisms, interface traps (N it ) at the Si-SiO 2 interface is the main contributor to the NBTI-induced ∆V T [6], [8].…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Impact of Interface Traps on Negative Capacitance Transistor: Device and Circuit Reliability

Prakash

Gupta

Pahwa

et al. 2020

IEEE J. Electron Devices Soc.

Self Cite

View full text Add to dashboard Cite

In this work, we investigate the impact of Si-SiO2 interface traps on the performance of negative capacitance transistor, which is a promising emerging technology that aims at achieving a steep sub-threshold slope. Interface traps induced degradation is well known to be one of the major concerns when it comes to reliability. We focus on investigating the impact of different interface trap concentrations on the figures of merit of both the devices and circuits. Our investigation is performed using TCAD models, which are well calibrated against 14 nm production quality FinFETs. This allows accurate analysis and modeling of the impact of NC on the electric field across the SiO2 layer. Then, the industry compact model of FinFET (BSIM-CMG) is fully calibrated to reproduce TCAD data. In addition, a physics-based NC model is integrated and solved self-consistently within the BSIM-CMG model in which TCAD data of NC-pFinFETs and NC-nFinFETs are also well matched. This allows studying how interface traps induced degradation can impact circuits. Our results demonstrate that the amplified electric field across the SiO2 layer within NC-pFinFET due to NC effect leads to a higher interface trap concentration. This, in turn, results in a larger degradation in the NC-pFinFET compared to its pFinFET counterpart -when both of these devices are operated at the same nominal supply voltage of the 14 nm node. However, at the same interface trap concentration, the NC-pFinFET always exhibits less degradation than the baseline pFinFET due to the former's better electrostatic integrity on account of voltage amplification effect. With respect to circuits, we study both Ring Oscillator (RO) and 6-T SRAM cell circuits. We show how the frequency of RO in the case of NC-FinFET is always less impacted by interface trap induced degradations compared to its counterpart FinFET-based RO. For 6-T SRAM cell, we demonstrate how the key reliability metrics such as hold noise margin, read noise margin, and write noise margin are also less impacted by the induced degradations in NC-FinFET SRAMs compared to the baseline FinFET SRAMs. This is because of the much better electrostatic integrity that NC provides.

show abstract

Section: Impact Of Interface Traps On Nc-pfinfetmentioning

confidence: 99%

Section: Impact Of Interface Traps On Circuitsmentioning

confidence: 99%

Section: A Impact Of Interface Traps On Ring Oscillator Performancementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Impact of Interface Traps on Negative Capacitance Transistor: Device and Circuit Reliability

Prakash

Gupta

Pahwa

et al. 2020

IEEE J. Electron Devices Soc.

Self Cite

View full text Add to dashboard Cite

show abstract

“…A compact model [6] based on BSIM-CMG is used for emerging NC-FinFET. Details on the used NC-FinFET modeling and FinFET device calibration with industrial measurements are available in [20] and [21], respectively.…”

Section: A Experimental Setupmentioning

confidence: 99%