A simulation framework for 3-dimension Networks-on-chip with different vertical channel density configurations

Ying, Haoyuan; Jaiswal, AK; Ghany, Mohamed A. Abd El; Hollstein, Thomas

doi:10.1109/ddecs.2012.6219030

Cited by 8 publications

(8 citation statements)

References 25 publications

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“…In our previous work [16], we have defined a generic scalable pseudo application (GSPA) which can generate random based complex traffic scenarios for NoCs evaluation. We took seven different V C density (from 12.5% to 87.5%, at 12.5% step) with random generated floor-planning as the topology various in an 8x8x4 network.…”

Section: B Experimental Resultsmentioning

confidence: 99%

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Communication-centric high level synthesis metrics for low vertical channel density 3-dimensional Networks-on-Chip

Ying

Hollstein

2012

7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)

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3D ICs have emerged as the promising solution for scalability, power consumption and performance demands of next generation Systems-on-Chip (SoC). Along with the advantages, it also imposes lots of challenges in terms of cost efficiency, technological reliability, power, thermal budget and so forth. Networks-on-chip (NoC) is thoroughly investigated in 2D SoC design as scalable interconnects, is also well relevant to 3D IC Design. The cost of moving from 2D to 3D for any application should be justified by the improvements in performance, power, latency and the utilization of Through-Silicon-Via (TSV). In this paper, we present a communication-centric metric for high level 3D NoCs synthesis, which can be used to improve the system performance and to reduce the link heat degree significantly by distributing the communication evenly in the system. We take several state-of-the-art benchmarks and the generic scalable pseudo application (GSPA) with different network sizes for experiments, by combining the simulated annealing algorithm with the presented metric. In comparison to the well-know metrics (dynamic communication energy aware and contention count), our metric can generally maintain the system performance and achieve up to 48% advantage on the aspect of Hottest Link Degree. All the experiments have been done in SystemC-RTL, which can achieve the cycle accuracy.

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Section: B Experimental Resultsmentioning

confidence: 99%

“…We engaged the all experiments by using GSNOC Simulator [16], XHiNoC [17] router, with 65 nm technology, the singlebit link (wire) on XY planar as 2.5 mm, 1 GHz clock frequency, 50% bandwidth injection rate, with SBSM routing algorithm, differently in 8x8x4, 8x4x4 and 4x4x4 network due to the limitation of the applications.…”

Section: A Experiments Setupmentioning

confidence: 99%

Communication-centric high level synthesis metrics for low vertical channel density 3-dimensional Networks-on-Chip

Ying

Hollstein

2012

7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)

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“…We engaged the all experiments by using GSNOC Simulator and XHiNoC [10], assuming the length of single-bit link (wire) on XY planar as 2.5 mm, the length of single-bit TSV is 20 µm, 1 GHz clock frequency, 25% bandwidth injection rate, within 8x8x4 and 4x4x4 networks. All the physical power parameters are extract from SYNOPSYS using the TSMCs 65 nm technology.…”

Section: Experimental Results Analysismentioning

confidence: 99%

“…Therefore, in this paper, we develop one GA based system optimization method, which can explore the design optimization possibilities and find out the more advanced system design setup through topology, routing algorithm, task mapping and tile placement. We took several unoptimized design setups through our GA and SA based optimization methods, and simulated the optimized design setups with our cycle accurate GSNOC framework [10]. The results have shown that the GA optimized design setups can achieve better performance and reduce the system communication cost in comparison to the SA optimized designs.…”

Section: Introductionmentioning

confidence: 99%

A genetic algorithm based optimization method for low vertical link density 3-dimensional Networks-on-Chip many core systems

2012

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The advantages of moving from 2-Dimensional Networks-on-Chip (NoCs) to 3-Dimensional NoCs for any application must be justified by the improvements in performance, power, latency and the overall system costs, especially the cost of Through-Silicon-Via (TSV). The trade-off between the number of TSVs and the 3D NoCs system performance becomes one of the most critical design issues. In this paper, we demonstrate a genetic algorithm (GA) based system optimization method, which can deliver the advanced system design setup through topology, routing algorithm, task mapping and tile placement. In comparison to the simulated annealing (SA) based design optimization method, our GA based method can achieve significant advantages. All the experiments have been done in GSNOC framework (written in SystemC-RTL), which can achieve the cycle accuracy and good flexibility.

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“…This paper describes the capabilities of a graphical user interface (GUI), wrapped around the GSNOC Simulator [1]. The GSNOC UI is written using the Qt UI framework [2].…”

Section: Introductionmentioning

confidence: 99%

GSNOC UI — A comfortable graphical user interface for advanced design and evaluation of 3-dimensional scalable Networks-on-Chip

Gottschling

Ying

2012

2012 International Conference on High Performance Computing &Amp; Simulation (HPCS)

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3D integrated circuit (IC) technology can be applied to the already known 2D Network-on-Chip (NoC) approach for System-on-Chips (SoCs). This resulting new approach brings advantages like higher integration density and better performance but also raises the question when the higher implementation costs are really profitable. To answer this question, for a lot of different cases, a framework was developed for simulating 3-dimensional (3D) NoCs, which provides results that are close to real applications and implementations. The framework is highly adaptable in terms of traffic scenarios, available memory, network size (including manual Through-Silicon-VIA (TSV) settings), routing algorithm, chip size and implementation technology. As the complexity of this framework increased in both, environment setup and available information, it was decided to build a graphical user interface (GUI) for an easy access to it. This user interface consists of a lucid configuration interface for generating the traffic scenarios and adjusting all necessary parameters for running a successful simulation. It further provides a frontend for observing the network during the running simulation. To give the user a good notion about the networks behavior, information about the processing elements (PEs) current state, the buffer utilization and the link utilization is displayed in a 2-dimensional (2D) and 3D model of the network. To check if predefined conditions to the energy budget and distributed memory demands are met, an automatically generated post simulation report summarizes all the gained information. This report includes the systems configuration, the buffer fill level, interconnect energy consumption and link utilization for each node and in total.

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A simulation framework for 3-dimension Networks-on-chip with different vertical channel density configurations

Cited by 8 publications

References 25 publications

Communication-centric high level synthesis metrics for low vertical channel density 3-dimensional Networks-on-Chip

Communication-centric high level synthesis metrics for low vertical channel density 3-dimensional Networks-on-Chip

A genetic algorithm based optimization method for low vertical link density 3-dimensional Networks-on-Chip many core systems

GSNOC UI — A comfortable graphical user interface for advanced design and evaluation of 3-dimensional scalable Networks-on-Chip

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A simulation framework for 3-dimension Networks-on-chip with different vertical channel density configurations

Cited by 8 publications

References 25 publications

Communication-centric high level synthesis metrics for low vertical channel density 3-dimensional Networks-on-Chip

Communication-centric high level synthesis metrics for low vertical channel density 3-dimensional Networks-on-Chip

A genetic algorithm based optimization method for low vertical link density 3-dimensional Networks-on-Chip many core systems

GSNOC UI &#x2014; A comfortable graphical user interface for advanced design and evaluation of 3-dimensional scalable Networks-on-Chip

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GSNOC UI — A comfortable graphical user interface for advanced design and evaluation of 3-dimensional scalable Networks-on-Chip