An increasing number of households is connected to the Internet via DSL or cable, for which home gateways are required. The optimization of these -caused by their large number -is a promising area for energy efficiency improvements. Since no power models for home gateways are currently available, the optimization of their power state is not possible. This paper presents PowerPi, a power consumption model for the Raspberry Pi which is used as a substitute to conventional home gateways to derive the impact of typical hardware components on the energy consumption. The different power states of the platform are measured and a power model is derived, allowing to estimate the power consumption based on CPU and network utilization only. The proposed power model estimates the power consumption resulting in a RMSE of less than 3.3%, which is slightly larger than the maximum error of the measurements of 2.5%.

Abstract. This paper presents an approach for rapidly adjustable embedded trace online monitoring of multi-core systems, called RETOM. Today, most commercial multi-core SoCs provide accurate runtime information through an embedded trace unit without affecting program execution. Available debugging solutions can use it to reconstruct the run offline, but usually for up to a few seconds only. RETOM employs a novel online reconstruction technique that makes the program run available outside the SoC and allows for evaluating a specification formulated in the stream-based specification language TeSSLa in real time. The necessary computing performance is provided by an FPGA-based event processing system. In contrast to other hardware-based runtime verification techniques, changing the specification requires no circuit synthesis and thus seconds rather than minutes or hours. Therefore, iterated testing and property adjustment during development and debugging becomes feasible while preserving the option of arbitrarily extending observation time, which may be necessary to detect rarely occurring errors. Experiments show the feasibility of the approach.

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3D integrated circuit (IC) technology can be applied to the already known 2D Network-on-Chip (NoC) approach for System-on-Chips (SoCs). This resulting new approach brings advantages like higher integration density and better performance but also raises the question when the higher implementation costs are really profitable. To answer this question, for a lot of different cases, a framework was developed for simulating 3-dimensional (3D) NoCs, which provides results that are close to real applications and implementations. The framework is highly adaptable in terms of traffic scenarios, available memory, network size (including manual Through-Silicon-VIA (TSV) settings), routing algorithm, chip size and implementation technology. As the complexity of this framework increased in both, environment setup and available information, it was decided to build a graphical user interface (GUI) for an easy access to it. This user interface consists of a lucid configuration interface for generating the traffic scenarios and adjusting all necessary parameters for running a successful simulation. It further provides a frontend for observing the network during the running simulation. To give the user a good notion about the networks behavior, information about the processing elements (PEs) current state, the buffer utilization and the link utilization is displayed in a 2-dimensional (2D) and 3D model of the network. To check if predefined conditions to the energy budget and distributed memory demands are met, an automatically generated post simulation report summarizes all the gained information. This report includes the systems configuration, the buffer fill level, interconnect energy consumption and link utilization for each node and in total.