A simple method to qualify the LDD structure against the early mode of hot-carrier degradation

Raychaudhuri, A.; Deen, M. J.; King, M.; Kwan, W. S.

doi:10.1109/16.477600

Cited by 28 publications

(8 citation statements)

References 18 publications

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“…Room temperature measurements also showed a clear lifetime dependence on width. This observation is new and is even contrary to statements made in previous publications [1] [10]. The smaller transistors were subject to a larger degree of degradation having verifiably shorter lifetimes.…”

Section: Results From 064µm/013µmcontrasting

confidence: 88%

Lifetime studies of 130nm nMOS transistors intended for long-duration, cryogenic high-energy physics experiments

Hoff¹,

Arora²,

Cressler³

et al. 2011

2011 IEEE Nuclear Science Symposium Conference Record

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Abstract-Future neutrino physics experiments intend to use unprecedented volumes of liquid argon to fill a time projection chamber in an underground facility. To increase performance, integrated readout electronics should work inside the cryostat. Due to the scale and cost associated with evacuating and filling the cryostat, the electronics will be unserviceable for the duration of the experiment. Therefore, the lifetimes of these circuits must be well in excess of 20 years. The principle mechanism for lifetime degradation of MOSFET devices and circuits operating at cryogenic temperatures is via hot carrier degradation. Choosing a process technology that is, as much as possible, immune to such degradation and developing design techniques to avoid exposure to such damage are the goals. This requires careful investigation and a basic understanding of the mechanisms that underlie hot carrier degradation and the secondary effects they cause in circuits. In this work, commercially available 130nm nMOS transistors operating at cryogenic temperatures are investigated. The results show that the difference in lifetime for room temperature operation and cryogenic operation for this process are not great and the lifetimes at both 300K and at 77K can be projected to more than 20 years at the nominal voltage (1.5V) for this technology.

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Section: Results From 064µm/013µmcontrasting

confidence: 88%

Lifetime studies of 130nm nMOS transistors intended for long-duration, cryogenic high-energy physics experiments

Hoff¹,

Arora²,

Cressler³

et al. 2011

2011 IEEE Nuclear Science Symposium Conference Record

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“…The data indicate that if the overlap capacitance is less than 0.29 fF/m, the hot-electron shift is anomalously large. This is a typical symptom of a phenomenon known as "prompt shift" [4], [5] and is indicative of too little doping in the source/drain regions beneath the gate and will also manifest itself in an increase in the resistance of the FET. Another aspect of inadequate overlap manifests itself in an apparent anomalously long effective channel length.…”

Section: Determination Of the Minimal Allowed Capacitancementioning

confidence: 98%

Spurious source/drain underlap of large junction area NFET's

Hook

1999

IEEE Trans. Semicond. Manufact.

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When a 0.35-m CMOS technology was introduced into manufacturing, a small fraction of the tested devices exhibited symptoms of source/drain underlap, despite the fact that all other monitors were well within the design control limits. Additional measurements showed variable overlap on various monitor structures on the same chip. The specific formulation of an HF wet clean was shown to be responsible for the underlapped devices, and the problem was eliminated by altering this process step. High-volume manufacturing data are presented to show the problem and the solution.Index Terms-Semiconductor device manufacture, semiconductor device reliability, semiconductor logic devices.

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“…In the other hand, the electric parameters of MOS transistor are more and more sensitive to defects bound to the presence of charges in the gate oxide and at the Si/SiO 2 interface [5]. The miniaturisation of MOS transistor (reduction of the channel length and oxide thickness) leads to the presence of higher electric fields, which are the source of degradation and lifetime reduction of the MOS transistor.…”

Section: Introductionmentioning

confidence: 99%

Electrical parameters degradation of power RF LDMOS device after accelerated ageing tests

Belaïd

Ketata

Masmoudi

et al. 2006

Microelectronics Reliability

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A simple method to qualify the LDD structure against the early mode of hot-carrier degradation

Cited by 28 publications

References 18 publications

Lifetime studies of 130nm nMOS transistors intended for long-duration, cryogenic high-energy physics experiments

Lifetime studies of 130nm nMOS transistors intended for long-duration, cryogenic high-energy physics experiments

Spurious source/drain underlap of large junction area NFET's

Electrical parameters degradation of power RF LDMOS device after accelerated ageing tests

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