A simple and effective design strategy to increase power conversion efficiency of linear charge pumps

Abstract

Summary This paper introduces a simple design strategy to increase the power efficiency of linear charge pumps. The technique exploits a voltage amplitude of the clock signal lower than the supply voltage to reduce the power conversion losses. The nominal output voltage is maintained unaltered by increasing the number of stages.

A Memory-Targeted Dynamic Reconfigurable Charge Pump to Achieve a Power Consumption Reduction in IoT Nodes

“…Therefore, power efficiency and power consumption are two fundamental aspects on which the CP design considerations are often focused. In literature several papers dealt with this topic [10]- [12], and are mainly focused on the well-known Dickson CP ( Fig.1) for its efficiency and advantages in an IC realization [13].…”

“…Considering, in particular, the Dickson CP power consumption, papers [10] and [11] report two optimized design strategies for power consumption reduction, taking into account the only bottom or both bottom and top plate parasite capacitances. On the other hand, in [12] authors explored the possibility to reduce power conversion losses by scaling the clock amplitude voltage, thus increasing the CPs number of stages to maintain the output voltage unaltered. Advantages of this strategy are also confirmed by the study reported in [14], which compares regulation schemes for CPs working in a wide range of clock frequency.…”

“…In the model of Fig. 2, VOUT and N/Cf represent the output voltage and the output impedance, respectively [12], being f the clock frequency, the input impedance, GIN, models the power consumption due to continuous switching of the stray capacitances and its value is given by…”

Current‐mode body‐biased switch to increase performance of linear charge pumps

“…Since their simple topologies are made‐up by switches and capacitors, they are amenable to be fully integrated and have been widely used in solid‐state electronic systems since the early 70s 1–4 . CPs are exploited in a large amount of applications, such as nonvolatile memories, SRAMs, switch controllers, LCD drivers and, more recently, energy harvesters 5–14 . In this last application, the design of a CP is a challenging task since it has to work with low input voltage (down to few hundreds of millivolts), while delivering at least few hundreds of nanowatts to the load with a high voltage conversion efficiency (VCE) 6 …”

“…To get rid of this drawback, different countermeasures exploiting the body (or bulk) junction voltages have been presented in literature. Based on how the bulk to source/drain voltage is managed, they can be distinguished in forward body biasing (FBB), backward body biasing (BBB), and dynamic body biasing (DBB) 3,8,13 . The use of these topologies results to be often limited by the inverse saturation currents and breakdown voltage of the bulk‐source/bulk‐drain junctions, as well as by the maximum available bulk voltage swing.…”