A Memory-Targeted Dynamic Reconfigurable Charge Pump to Achieve a Power Consumption Reduction in IoT Nodes

Abstract

Targeting the more recently adopted low-power memories for data-logging operation in IoT nodes, this paper presents a simple reconfigurable dual-branch cross-coupled charge pump (CP) topology in which clock amplitude scaling and modulation of the number of stages are exploited to improve power efficiency and/or change the output voltage without degrading speed performance. The proposed solution allows a reduction of the power conversion losses, maintaining speed, maximum output voltage and silicon area unaltered as compared to the conventional charge pump. Post-layout simulation results confirm the effectiveness of the proposed topology which can be adapted to any other kind of linear charge pump.

The Dickson Charge Pump as a Signal Amplifier

“…whose values coincides with the switching impedance of the pumping capacitance batch and, according to [47], 3 the CP self-capacitance, respectively. The output impedance introduces an intrinsic pole, which defines the frequency limits of the CP (i.e., the bandwidth of the block itself).…”

“…1 is better modeled by the small signal equivalent circuit in Fig. 5, since, as explained below, the output resistance can be different orders of magnitude lower than the value in SSL given 3 The function A(N ) was introduced in [47] and its value is here reported…”

Low Voltage Switched-Capacitive-Based Reconfigurable Charge Pumps for Energy Harvesting Systems: An Overview

“…As a numerical example, a double in the number of the stage (N2 = 2N1) will result in a 4 times longer settling time (Tsettling2 = 4Tsettling1) assuming all other parameters remain unchanged. Such speed degradation is unfavorable in the certain load that requires fast system response, for example, IoT nodes for data logging [76]. Hence, the N tuning is usually implemented in association with frequency tuning to overcome the speed reduction.…”

“…To mitigate this issue, the gate control circuit is usually implemented with the adaptive clock gain scheme to provide a proper gate biasing for the CTS. The work [76] proposed a dynamic reconfigurable linear CP that exploits the clock amplitude reduction to improve the circuit PCE, while maintaining the speed. The clock amplitude reduction is achieved by implementing a clock amplitude reducer (CKAR) where Vclk is set to Vdd in transparency mode or half Vdd in reduction mode.…”

Signal Amplification by Means of a Dickson Charge Pump: Analysis and Experimental Validation

“…Design strategies as a function of the output capacitive load were proposed in [14][15][16] with the goal to speed-up the CP and decrease output voltage ripple in low-output current applications. In [17], the suggested design strategy aimed to decrease switching power losses and increase the power conversion efficiency, and a topology based on this strategy was introduced in [18] targeting solid-state memories.…”