A simple alternative for storage allocation in high-level synthesis

Aloqeely, M.

doi:10.1109/iscas.1998.705289

Cited by 2 publications

(4 citation statements)

References 10 publications

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“…Aloqeely, later, proposed [5] Sequential FIFO Memory (SFM) as an alternative for RAM. Here, the problem of mapping variables to SFMs is claimed to be tractable, while mapping variables to other similar structures [6] was intractable.…”

Section: A Related Workmentioning

confidence: 99%

Storage-allocation to sequential structures in High-Level Synthesis-assisted prototyping

Kumar

Maity

Patkar

2014

2014 IEEE 32nd International Conference on Computer Design (ICCD)

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Algorithm-to-hardware High-Level Synthesis (HLS) tools are becoming increasingly practical, particularly the domain specific approaches to HLS. Storage allocation is an important step in HLS where variables are mapped to onchip storage structures (OSS). HLS flows almost exclusively do this allocation to random access OSS whereas custom designers often pick from a repertoire of intuitive algorithmappropriate OSS. In this work, revisiting a sparsely addressed problem of storage allocation to sequential access OSS, we report tractable algorithms for storage allocation to three kinds of sequential access style memories-Queue, Queue-Read Sequential-Write memory (QRSWM), and Sequential-Read Sequential-Write memory (SRSWM)-suitable for domains such as signal processing and matrix computations. A basic C to Verilog HLS flow was developed integrating these new allocations options to evaluate their impact on the overall design metrics of interest such as area and power. On application cases such as matrix multiplication and 2D/3D wavelet filtering, a comparison vis-a-vis RAM shows significant improvements in power consumption when targeting TSMC 0.18µ technology.

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Section: A Related Workmentioning

confidence: 99%

Storage-allocation to sequential structures in High-Level Synthesis-assisted prototyping

Kumar

Maity

Patkar

2014

2014 IEEE 32nd International Conference on Computer Design (ICCD)

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“…However, some researchers have argued that the built-in address decoder which is present in the conventional RAM model restricts the freedom of memory system optimizers to arrive at an optimal memory architecture for a given al- gorithm [1,3,11]. This is particularly true for applicationspecific integrated circuits where the address sequences are deterministic and often regular.…”

Section: Related Workmentioning

confidence: 99%

“…We propose a Shift Register based Address Generator (SRAG) architecture, as shown in Figure 5, which can generate many regular address sequences, especially those found in block-based image processing algorithms. This design is an improvement on the Sequential FIFO memory (SFM) proposed by Aloqeely [1]. SFM works on the same principle as a RAM but the address decoder is replaced by two single-bit shift registers, one for read and the other for write ( Figure 6).…”

Section: Shift Register Based Address Generator Architecturementioning

confidence: 99%

“…In this paper, we examine the possible impact on area and performance of memory access related circuitry in eliminating the row and column address decoders from the memory by incorporating any necessary decoding with the address generation circuit. The novel contributions of this paper are: (1) to propose an "address decoder-decoupled memory" model that separates the built-in address decoder from memory and incorporates the address generation and any address decoding logic into one or more finite state machines (FSMs); (2) to evaluate such a generic model for address sequencing in the context of circuit synthesis and assess its limitations; (3) to propose a shift register based architecture with "two-hot" encoding as an efficient implementation of such FSMs for regular address sequences; (4) to compare the proposed approach with those using conventional address counter/decoding methods in terms of area and performance. This paper is organized as follows.…”

Section: Introductionmentioning

confidence: 99%

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Performance-area trade-off of address generators for address decoder-decoupled memory

Hettiaratchi

Cheung

Clarke

Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition

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Multimedia applications are characterized by a large number of data accesses and complex array index manipulations. The built-in address decoder in the RAM memory model commonly used by most memory synthesis tools, unnecessarily restricts the freedom of address generator synthesis. Therefore a memory model in which the address decoder is decoupled from the memory cell array is proposed. In order to demonstrate the benefits and limitations of this alternative memory model, synthesis results for a Shift Register based Address Generator that does not require address decoding are compared to those for a counter-based address generator that requires address decoding. Results show that delay can be nearly halved at the expense of increased area.

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A simple alternative for storage allocation in high-level synthesis

Cited by 2 publications

References 10 publications

Storage-allocation to sequential structures in High-Level Synthesis-assisted prototyping

Storage-allocation to sequential structures in High-Level Synthesis-assisted prototyping

Performance-area trade-off of address generators for address decoder-decoupled memory

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