Performance-area trade-off of address generators for address decoder-decoupled memory

Hettiaratchi, Sambuddhi; Cheung, Peter Y. K.; Clarke, Thomas

doi:10.1109/date.2002.998407

Cited by 6 publications

(5 citation statements)

References 13 publications

(19 reference statements)

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“…The methodology is directly applicable to address generator synthesis methods which require an expanded address sequence, such as counter based methods [6], shift register based methods [9] and finite state machine based methods [9].…”

Section: Discussionmentioning

confidence: 99%

Energy efficient address assignment through minimized memory row switching

Hettiaratchi

Cheung

Clarke

2002

Proceedings of the 2002 IEEE/ACM International Conference on Computer-Aided Design - ICCAD '02

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Data transfer intensive applications consume a significant amount of energy in memory access. The selection of a memory location from a memory array involves driving row and column select lines. A signal transition on a row select line often consumes significantly more energy than a transition on a column select line. In order to exploit this difference in energy consumption of row and column select lines, we propose a novel address assignment methodology that aims to minimize high energy row transitions by assigning spatially and temporally local data items to the same row. The problem of energy efficient address assignment has been formulated as a multi-way graph partitioning problem and solved with a heuristic. Our experiments demonstrate that our methodology achieves row transition counts very close to the optimum and that the methodology can, for some examples, reduce row transition count by 40-70% over row major mapping. Moreover, we also demonstrate that our methodology is capable of handling access sequences with over 15 million accesses in moderate time.

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Section: Discussionmentioning

confidence: 99%

Energy efficient address assignment through minimized memory row switching

Hettiaratchi

Cheung

Clarke

2002

Proceedings of the 2002 IEEE/ACM International Conference on Computer-Aided Design - ICCAD '02

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“…One of them is presented by Hetti. 15 The author examines the impact on area and performance of memory accesses related circuitry by using simplified architectures for the address generation circuit, but this technique is applicable only on deterministic and regular address sequences.…”

Section: Sequencer Optimizations For Performancementioning

confidence: 99%

“…depending of timing and area constraints. 15 Data processing can easily be speed up through pipelining and other forms of parallelism. In the simpler case where the memory accesses can be determined statically, the compiler can schedule the order in which the accesses should occur.…”

Section: Sequencer Based Approachesmentioning

confidence: 99%

<title>Bounded budgeted parallel architecture versus control dominated architecture for hazard data-signal processor synthesis</title>

2005

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Multimedia applications such as video and image processing are often characterized by a large number of data accesses (i.e. RAM accesses). In many digital signal-processing applications, the array access patterns are regular and periodic. In these cases, optimized Pipelined Memory Access Controllers can be generated. This technique is used to improve the pipeline access mode to RAM by creating specialized hardware components for generating addresses and packing and unpacking data items. In this paper we focus on the design, implementation and validation of memory interfacing modules that can be automatically generated from a behavioural synthesis tool and which can efficiently handle predictable address patterns as well as unpredictable ones (dynamic address computations) in a pipeline way. We also analyze the benefits of balancing dynamic address computations from datapath to specialized computation units placed in the memory controller, optimizing bitwise of operators and data locality i.e. reducing the power consumption.

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“…For example, in [19], the impact on area and performance of memory access related circuitry using simplified architectures for address generation is examined. This technique is applicable only on deterministic and regular address sequences.…”

Section: Datapath and Memory Unit Interfacingmentioning

confidence: 99%

“…1. The sequencer can be implemented using dedicated counters or shift registers depending on the constraints [19].…”

Section: Datapath and Memory Unit Interfacingmentioning

confidence: 99%

Dynamic Memory Access Management for High-Performance DSP Applications Using High-Level Synthesis

Gal

Casseau²,

Huet³

2008

IEEE Trans. VLSI Syst.

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International audienceMultimedia applications such as video and image processing are often characterized by a huge number of data accesses. In many digital signal processing applications, array access patterns are regular and periodic. In these cases, optimized architectures using pipelined memory access controllers can be generated. In this paper, we focus on implementing memory interfacing modules that can be automatically generated from a high-level synthesis tool and which can efficiently handle predictable address patterns as well as random ones (i.e., dynamic address computations). The benefits of balancing dynamic address computations from datapath to dedicated computation units in the memory controller is also analyzed as well as operator bitwidth optimization and data locality to save power consumption and reduce latency

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Performance-area trade-off of address generators for address decoder-decoupled memory

Cited by 6 publications

References 13 publications

Energy efficient address assignment through minimized memory row switching

Energy efficient address assignment through minimized memory row switching

<title>Bounded budgeted parallel architecture versus control dominated architecture for hazard data-signal processor synthesis</title>

Dynamic Memory Access Management for High-Performance DSP Applications Using High-Level Synthesis

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