A silicon compiler for digital signal processing: Methodology, implementation, and applications

Yassa, F.; Jasica, J.R.; Hartley, Richard; Noujaim, S.E.

doi:10.1109/proc.1987.13879

Cited by 52 publications

(6 citation statements)

References 8 publications

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“…Examples of academic efforts include ADAM [38], [47], HAL [73], MIMOLA [63], Hercules/Hebe [25], [26], [56], and Hyper/Hyper-LP [10], [78]. Industry efforts include Cathedral and its successors [27], Yorktown Silicon Compiler [11], and BSSC [93], among many others. Like CMU-DA, these tools typically decompose the synthesis task into a few steps, including code transformation, module selection, operation scheduling, datapath allocation, and controller generation.…”

Section: A Early Effortsmentioning

confidence: 99%

High-Level Synthesis for FPGAs: From Prototyping to Deployment

Cong

Liu

Neuendorffer

et al. 2011

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

653

272

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Abstract-Escalating system-on-chip design complexity is pushing the design community to raise the level of abstraction beyond register transfer level. Despite the unsuccessful adoptions of early generations of commercial high-level synthesis (HLS) systems, we believe that the tipping point for transitioning to HLS methodology is happening now, especially for field-programmable gate array (FPGA) designs. The latest generation of HLS tools has made significant progress in providing wide language coverage and robust compilation technology, platform-based modeling, advancement in core HLS algorithms, and a domain-specific approach. In this paper, we use AutoESL's AutoPilot HLS tool coupled with domain-specific system-level implementation platforms developed by Xilinx as an example to demonstrate the effectiveness of state-of-art C-to-FPGA synthesis solutions targeting multiple application domains. Complex industrial designs targeting Xilinx FPGAs are also presented as case studies, including comparison of HLS solutions versus optimized manual designs. In particular, the experiment on a sphere decoder shows that the HLS solution can achieve an 11-31% reduction in FPGA resource usage with improved design productivity compared to hand-coded design.Index Terms-Domain-specific design, field-programmable gate array (FPGA), high-level synthesis (HLS), quality of results (QoR).

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Section: A Early Effortsmentioning

confidence: 99%

High-Level Synthesis for FPGAs: From Prototyping to Deployment

Cong

Liu

Neuendorffer

et al. 2011

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

653

272

View full text Add to dashboard Cite

show abstract

“…The bit-serial compilers FIRST [Denyer84], Inpact [Yassa87], and Cathedral I [Jain86] are applicable to both FIR and IIR filters but are mostly useful for low sample rate filters such as in speech, audio and telecommunication applications [Ginderdeuren86]. Microcoded bit-parallel compilers [Rabaey85,Ruetz86] have also been used for these low sample rate applications.…”

Section: Architectural Reviewmentioning

confidence: 99%

Anatomy of a Silicon Compiler

Brodersen¹

1992

The Kluwer International Series in Engineering and Computer Science

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“…The custom implementation is substantially smaller (by a factor of approximately two and a half) than the equivalent filter based on full two's complement multipliers and adders. The area/speed performance of this design compares favorably with those in [5,12,16,18,19] when normalized for the older technology used in the present case. In particular, the architecture in [19], based on the FIRGEN compiler [8], also uses canonic signed-digit (CSD) coefficients.…”

Section: Custom Implementationmentioning

confidence: 79%

An efficient FIR filter architecture

Evans

1993 IEEE International Symposium on Circuits and Systems

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A silicon compiler for digital signal processing: Methodology, implementation, and applications

Cited by 52 publications

References 8 publications

High-Level Synthesis for FPGAs: From Prototyping to Deployment

High-Level Synthesis for FPGAs: From Prototyping to Deployment

Anatomy of a Silicon Compiler

An efficient FIR filter architecture

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