A Sign-Equality-Based Background Timing-Mismatch Calibration Algorithm for Time-Interleaved ADCs

Kang, Hyun-Wook; Hong, Hyeok-Ki; Park, Sanghoon; Kim, Ki‐Jin; Ahn, Kwang–Ho; Ryu, Seung‐Tak

doi:10.1109/tcsii.2016.2530819

Cited by 29 publications

(17 citation statements)

References 6 publications

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“…Error estimation using derivative is a real-time and efficient algorithm that has been continuously explored [19,24]. The principle is shown in Fig.…”

Section: Timing Mismatch Estimationmentioning

confidence: 99%

“…The e n is the sampling error betweenŷ n and y n , and s n represents the instantaneous derivative of y n . For the derivative-based Least Mean Square (LMS) calibration algorithm in [19], the timing mismatch can be estimated using the e n and the s n (or at least know in which direction the mismatch should be corrected [24]) as follows.…”

Section: Timing Mismatch Estimationmentioning

confidence: 99%

“…The sub- [31]. In a similar way, the reference channel sign judging is realized by multiplying r sign and e sign [24]. The adjacent sampled points that adopted here to calculate the derivative r sign are all from the reference channel.…”

Section: Timing Mismatch Estimationmentioning

confidence: 99%

“…Many techniques have been developed in digital domain for timing mismatch calibration. Most of these leading methods for error estimation are featured by using channel cross-correlation [21,22,23] or introducing reference channel [24,25,26], while most of the compensation methods are based on Taylor expansion [27,28,29] or filter [30]. Most of the calibration methods mentioned above use dividers, multipliers, and differentiators, which consumed high hardware and large power.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Calibration of timing mismatch in TIADC based on monotonicity detecting of sampled data

Yin

Sun

Chen

et al. 2020

IEICE Electron. Express

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In this paper, a calibration method aiming at the timing mismatch existing in the TIADC (Time-Interleaved Analog-to-Digital Converter) is proposed. Monotonicity detecting of the sampled data is employed to estimate the mismatch error, in which only additive operation is involved. Besides that, an improved Taylor expansion method is used to compensate the mismatch error. The processes of the estimation and the compensation are designed to constitute an adaptive loop, so that the calibration can be run in real-time. Compared with other approaches, this method consumes less hardware resources and has a good calibration result.

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“…Error estimation using derivative is a real-time and efficient algorithm that has been continuously explored [19,24]. The principle is shown in Fig.…”

Section: Timing Mismatch Estimationmentioning

confidence: 99%

Section: Timing Mismatch Estimationmentioning

confidence: 99%

Section: Timing Mismatch Estimationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Calibration of timing mismatch in TIADC based on monotonicity detecting of sampled data

Yin

Sun

Chen

et al. 2020

IEICE Electron. Express

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show abstract

“…Some techniques have been developed in digital domain for timing mismatch calibration. However, most of these techniques [11,12,13,14,15,16] are derived assuming that the input signal is limited to the first Nyquist band (NB), and cannot be directly employed in the under-sampling TIADCs that are capable of sampling input signal located in the higher NB. Although some technologies can work for higher NB input, various problems still exist.…”

Section: Introductionmentioning

confidence: 99%

A channel multiplexing digital calibration technique for timing mismatch of time-interleaved ADCs

Yin

Liu

Chen

et al. 2019

IEICE Electron. Express

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This paper presents an all-digital calibration technique for timeinterleaved ADC (TIADC) timing mismatch. The calibration architecture is based on a channel multiplexing architecture. For a M-channel TIADC, only one centralized calibration module is needed. Timing mismatches between channels are estimated by correlating the adjacent channel's outputs and a compensation algorithm based on the one-order five-point differentiator is employed to suppress the mismatches. Compared with conventional parallel calibration architecture, the proposed calibration architecture works well in higher Nyquist bands (NB) with high-scalability. The hardware consumption does not increase linearly with the number of sub-ADCs.

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An 18‐bit 1‐GS/s time interleaved analog‐to‐digital converter with timing skew calibration based on an adaptive genetic algorithm

Zhao

Zhang

et al. 2023

Circuit Theory & Apps

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SummaryA foreground calibration method for timing skews of the time interleaved analog‐to‐digital converter (TIADC) system is proposed in this paper. In this method, the adaptive genetic algorithm (AGA) is used to replace the traditional least mean square (LMS) method to detect the timing skews, and the variable delay lines are used to calibrate the timing skews. This method can accomplish the detection and calibration of positive and negative timing skews, and the reference channels are not required. In addition, compared with other methods, this method has higher detection speed and detection accuracy. In this paper, a four‐channel 18‐bit 1‐GS/s TIADC system is modeled, and the performance of the proposed method is further verified. The results show that the convergence speed and the calibration accuracy of this method are higher, the signal‐to‐noise ratio (SNR) of the TIADC system is improved by 65.9 dB after calibration, and this method is also effective when the frequency of the input signal is close to the Nyquist frequency.

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A Sign-Equality-Based Background Timing-Mismatch Calibration Algorithm for Time-Interleaved ADCs

Cited by 29 publications

References 6 publications

Calibration of timing mismatch in TIADC based on monotonicity detecting of sampled data

Calibration of timing mismatch in TIADC based on monotonicity detecting of sampled data

A channel multiplexing digital calibration technique for timing mismatch of time-interleaved ADCs

An 18‐bit 1‐GS/s time interleaved analog‐to‐digital converter with timing skew calibration based on an adaptive genetic algorithm

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