Abstract:Abstract-In this paper a frequency quadrupler circuit, integrated with a commercially available SiGe HBT technology (fT /fmax ≈ 80 / 90 GHz) is presented. The quadrupler consists of two Gilbert cell mixers stacked as squarers. The measured maximum conversion gain is 0.6 dB for an input level of -9 dBm. The circuit is optimized for M-QAM carrier recovery, and the performance was tested by applying QPSK and 16QAM modulated signals with 4 Gbit/s data rate at the input. Both experimental and simulated results are … Show more
“…Thereby a tuned characteristic is achieved for an input frequency of 5 GHz and an output frequency of 20 GHz. Detailed description of the frequency quadrupler circuit can be found in [5]. The frequency divider IC is a static divide-by-four frequency divider in master-slave flip-flop topology.…”
Abstract-In this work, we present a synchronous receiver architecture utilizing analog carrier recovery, to be used in multi-gigabit wireless communication systems. Carrier phase and frequency synchronization in the analog receiver drastically reduces cost and simplifies the system design by enabling the usage of 1-bit resolution analog to digital converters (ADC). The focus of this work is mainly the analog carrier recovery, which forms the basis of the proposed receiver. Simulation and experimental results are presented, demonstrating the applicability of the presented analog receiver concept for multi-gigabit communication links.
“…Thereby a tuned characteristic is achieved for an input frequency of 5 GHz and an output frequency of 20 GHz. Detailed description of the frequency quadrupler circuit can be found in [5]. The frequency divider IC is a static divide-by-four frequency divider in master-slave flip-flop topology.…”
Abstract-In this work, we present a synchronous receiver architecture utilizing analog carrier recovery, to be used in multi-gigabit wireless communication systems. Carrier phase and frequency synchronization in the analog receiver drastically reduces cost and simplifies the system design by enabling the usage of 1-bit resolution analog to digital converters (ADC). The focus of this work is mainly the analog carrier recovery, which forms the basis of the proposed receiver. Simulation and experimental results are presented, demonstrating the applicability of the presented analog receiver concept for multi-gigabit communication links.
“…By this means, a tuned behavior with an input frequency of 5 GHz and an output frequency of 20 GHz is achieved. The measured 3 dB bandwidth extends from 19 to 22.2 GHz at the output with a conversion gain of 0.5 dB at an input power of −9 dBm [11]. Fig.…”
This paper presents a hardware efficient receiver architecture, to be used in low-cost, ultra-high rate 60 GHz wireless communication systems. The receiver utilizes a simple, feed-forward carrier recovery concept, performing phase and frequency synchronization in the analog domain. This enables 1-bit baseband processing without a need of ultra-high speed and high precision analog-to-digital conversion, offering a strong simplification of the system architecture and comparatively low power consumption. In a first prototype implementation, the receiver is realized in a low-cost SiGe technology as two separate ICs: the 60 GHz/5 GHz downconverter, and the intermediate frequency synchronous demodulator. The simple synchronous reception concept is experimentally validated for up to 3.5 Gbit/s data rate, which constituted the limit of the existing experimental setup. Furthermore, the downconverter demonstrates that low-cost technologies (fop/fmax ~ 0.75) can be used to realize short-range data links at 60 GHz, with low-noise amplifiers in a more performant technology as needed.
“…In this FS structure, the low‐frequency FS is operated at the subharmonic of the desired frequency, and the target frequency is generated by the frequency multiplier after the low‐frequency FS. Most of the published ×4 frequency multipliers are frequency doublers [1, 2], which mean that an additional stage has to be used to get higher frequency multiplication factor. A frequency quadrupler also can be formed with a single‐stage quadrupler [3–5], it exploits the nonlinearity of active devices to generate harmonics of the input signal, and this approach may require high‐Q passive LC circuits, which are difficult to build on lossy silicon substrate.…”
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