A Si bipolar 5-Gb/s 8:1 multiplexer and 4.2-Gb/s 1:8 demultiplexer

Using our 0.2 and 0.3 μm AlGaAs/GaAs/AlGaAs quantum well HEMT technology, we have developed a chip set for 20–40 Gbit/s fiber-optical digital transmission systems. In this paper we describe nine analog and digital receiver ICs: a 22 GHz high-gain transimpedance amplifier, a 20 Gbit/s OEIC front-end optical receiver, a 25 Gbit/s automatic-gain-control amplifier, a limiting amplifier with a differential gain of 26 dB and a bandwidth of 27.7 GHz, a 20–40 Gbit/s clock recovery, a 20 Gbit/s low-power Master-Slave-D-Flipflop with 24 mW power dissipation, a parallel data decision and a 1:4 demultiplexer, both for bit rates of 40 Gbit/s, and a 30 GHz static frequency divider, respectively. All chips were characterized on wafers with 50 Ω coplanar test probes.

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A Si bipolar 5-Gb/s 8:1 multiplexer and 4.2-Gb/s 1:8 demultiplexer

Cited by 3 publications

References 6 publications

A 3.6-Gb/s 340-mW 16:1 pipe-lined multiplexer using 0.18 /spl mu/m SOI-CMOS technology

A 3.6-Gb/s 340-mW 16:1 pipe-lined multiplexer using 0.18 /spl mu/m SOI-CMOS technology

A 3.6 Gb/s 340 mW 16:1 pipe-lined multiplexer using SOI-CMOS technology

20–40 Gbit/s GaAs-HEMT CHIP SET FOR OPTICAL DATA RECEIVER

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