A Semi-Formal Technique to Generate Effective Test Sequences for Reconfigurable Scan Networks

Cantoro, Riccardo; Damljanovic, Aleksa; Reorda, M. Sonza; Squillero, Giovanni

doi:10.1109/itc-asia.2018.00020

Cited by 2 publications

(10 citation statements)

References 10 publications

(24 reference statements)

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“…At the same time, the new algorithm is almost always faster than its predecessor. Experimental results on a set of benchmarks [15] demonstrate that the approach is able to generate test sequences orders of magnitude shorter than those reported in [14], [11] and [13], while always keeping the computational cost under control.…”

Section: Introductionmentioning

confidence: 94%

“…In the proposed approach, the RSN of IEEE 1687 is modeled as a finite state automaton as in [14]. Each state corresponds to a configuration, that is, a determinate state of SIBs and SMs in the network; the input alphabet corresponds to reconfiguration operations; the output symbols are the lengths of the active paths, as this is an easily observable characteristic [11].…”

Section: Proposed Approachmentioning

confidence: 99%

“…To demonstrate the difference in the Test Sequence Generation procedure between this approach and [14], we can use the network shown in Fig. 2.…”

Section: B Search Algorithmmentioning

confidence: 99%

“…Its main advantage lies in its ability to always produce a solution, no matter the RSN complexity, while the quality of the produced result (i.e., the duration of the resulting test) is never too far from the optimum, when the latter can be computed, and it is often lower than the one produced by the method described in [11]. In [14] we first modeled the RSN as a Finite State Automaton (FSA), and then we proposed a semi-formal method able to deal with larger and more complex circuits producing a test sequence able to detect any permanent fault affecting the reconfigurable modules, but whose duration is lower than the one of the test sequences previously generated by the heuristic solutions.…”

Section: Introductionmentioning

confidence: 99%

“…In this paper we further extended the approach of [14] by rewriting the test generator. The new algorithm minimizes the number of costly operations, postponing and compacting them, while it still guarantees to reach complete fault coverage.…”

Section: Introductionmentioning

confidence: 99%

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A New Technique to Generate Test Sequences for Reconfigurable Scan Networks

Cantoro

Damljanovic

Reorda

et al. 2018

2018 IEEE International Test Conference (ITC)

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Nowadays, industries require reliable methods for accessing the instrumentations embedded within semiconductor devices. The situation led to the definition of standards, such as the IEEE 1687, for designing the required infrastructures, and the proposal of techniques to test them. So far, most of the test-generation approaches are either too computationally demanding to be applied in complex cases, or too approximate to yield high-quality tests. This paper exploits a recent idea: the state of a generic reconfigurable scan chain is modeled as a finite state automaton and a low-level fault, as an incorrect transition; it then proposes a new algorithm for generating a functional test sequence able to detect all incorrect transitions far more efficiently than previous ones. Such an algorithm is based on a greedy search, and it is able to postpone costly operations and eventually minimize their number. Experimental results on ITC'16 benchmarks demonstrate that the proposed approach is broadly applicable; has limited computational requirements; and the test sequences are order of magnitudes shorter than the ones previously generated by approximate methodologies.

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