A New Technique to Generate Test Sequences for Reconfigurable Scan Networks

Abstract

Nowadays, industries require reliable methods for accessing the instrumentations embedded within semiconductor devices. The situation led to the definition of standards, such as the IEEE 1687, for designing the required infrastructures, and the proposal of techniques to test them. So far, most of the test-generation approaches are either too computationally demanding to be applied in complex cases, or too approximate to yield high-quality tests. This paper exploits a recent idea: the state of a generic reconfigurable scan chain is modeled as a finite state automaton and a low-level fault, as an incorrect transition; it then proposes a new algorithm for generating a functional test sequence able to detect all incorrect transitions far more efficiently than previous ones. Such an algorithm is based on a greedy search, and it is able to postpone costly operations and eventually minimize their number. Experimental results on ITC'16 benchmarks demonstrate that the proposed approach is broadly applicable; has limited computational requirements; and the test sequences are order of magnitudes shorter than the ones previously generated by approximate methodologies.

Post-Silicon Validation of IEEE 1687 Reconfigurable Scan Networks

“…The proposed methodology is based on previous work focused on generating efficient patterns to perform end-ofmanufacturing test for RSNs [3]. The detection mechanism introduced first in [4] and then adopted in several works [5], [6] has been modified to reduce significant overhead and has been made more suitable for addressing the presented problem.…”

“…4c). (1,3) n 122 (2,3) n 2 (0,0) n 3 (0,2) n 31 (1,1) n 32 (1,2) n 33 (1,1) n 1 (0,3) n 12 ( IV. EXPERIMENTS We developed a prototypical tool, able to build an internal simplified RSN model by reading the ICL description of the network.…”