A Self-Tuning IoT Processor Using Leakage-Ratio Measurement for Energy-Optimal Operation

Lee, Jeongsup; Miyoshi, Seiji; Kawaminami, Masaru; Blaauw, David; Sylvester, Dennis; Zhang, Yiqun; Dong, Qing; Lim, Wootaek; Saligane, Mehdi; Kim, Yejoong; Jeong, Seokhyeon; Lim, Jongyup; Yasuda, Makoto

doi:10.1109/jssc.2019.2939890

Cited by 39 publications

(24 citation statements)

References 20 publications

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“…For this purpose, the dependence of the trip points of a CMOS inverter on the aspect ratios of the pull-up and pull-down devices, given by Equation (5), is leveraged in the post-fabrication SDC ( Figure 3a) procedure proposed in [16], which makes it possible to tune the effective aspect ratio of either the pull-up or the pull-down branch by enabling/disabling binary weighted 2 i W min transistors in parallel to first inverters of the DM amplifier, based on a 8-bit calibration code b i,n with…”

Section: Process Variations and Mismatchmentioning

confidence: 99%

“…The pull-up (pull-down) network of the calibration inverter can be connected to the supply (to ground) through a pMOS (nMOS) power gating switch. When the pMOS (nMOS) gating switch is on, the pMOS (nMOS) of the calibration inverter, with width W n (W p ) is enabled and connected in parallel to the nMOS (pMOS) device in the first stage of the DM amplifier, thus effectively increasing its width and significantly reducing (increasing) its trip point according to Equation (5).…”

Section: Dynamic Digital Calibration (Ddc)mentioning

confidence: 99%

“…Small dimensions and low power consumption are critical requirements of pervasive, (nearly) energy autonomous sensor nodes for the Internet of Things (IoT) [1][2][3][4], Figure 1a. While digital circuits can be extremely power-and area-efficient thanks to geometry, voltage and frequency scaling [5], analog circuits are still lagging behind and their performance can be severely degraded in new CMOS technologies nodes due to the limited voltage headroom, high process variability and poor analog characteristics of nanoscale transistors [6].…”

Section: Introductionmentioning

confidence: 99%

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Dynamic and Static Calibration of Ultra-Low-Voltage, Digital-Based Operational Transconductance Amplifiers

et al. 2020

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The calibration of the effects of process variations and device mismatch in Ultra Low Voltage (ULV) Digital-Based Operational Transconductance Amplifiers (DB-OTAs) is addressed in this paper. For this purpose, two dynamic calibration techniques, intended to dynamically vary the effective strength of critical gates by different modulation strategies, i.e., Digital Pulse Width Modulation (DPWM) and Dyadic Digital Pulse Modulation (DDPM), are explored and compared to classic static calibration. The effectiveness of the calibration approaches as a mean to recover acceptable performance in non-functional samples is verified by Monte-Carlo (MC) post-layout simulations performed on a 300 mV power supply, nW-power DB-OTA in 180 nm CMOS. Based on the same MC post-layout simulations, the impact of each calibration strategy on silicon area, power consumption, and OTA performance is discussed.

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Section: Process Variations and Mismatchmentioning

confidence: 99%

Section: Dynamic Digital Calibration (Ddc)mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Dynamic and Static Calibration of Ultra-Low-Voltage, Digital-Based Operational Transconductance Amplifiers

et al. 2020

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“…However, either way, it will adversely increase the leakage mechanisms of volume depletion and L-BTBT which deteriorates the functionality and scaling of JLFETs. Thus, there exhibits a trade-off between the subthreshold swing and OFF-state performance of the GP-JLFET but the reduced short-channel effects and the superior OFF-state performance even for the sub-10 nm regime with a significant ION/IOFF ratio makes the proposed device quite lucrative for the low-power and low-leakage applications where the ultra-low power consumption is highly desirable to support a long battery life essential for their wireless sensor nodes [17], [18]. The transfer characteristics of GP-JLFET and SOI-JLFET for various drain biases at a gate length of 7 nm are shown in Fig.…”

Section: Scalability Analysis Of Gp-jlfetmentioning

confidence: 99%

“…Thus, the employment of a GP at a shallow depth inside the high-K BOX efficiently reduces the aforementioned leakage mechanisms and short channel effects and improves the scalability of the SOI-JLFET to the sub-10 nm regime. This makes the proposed device quite lucrative for the lowpower and low-leakage applications, specifically for internet of things (IoT) and automotive applications where the ultra-low power consumption is highly desirable to support a long battery life essential for their wireless sensor nodes [17], [18].…”

Section: Introductionmentioning

confidence: 99%

Sub-10 nm Scalability of Junctionless FETs Using a Ground Plane in High-K BOX: A Simulation Study

Jain

Kumar

2020

IEEE Access

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The leakage mechanisms of inefficient volume depletion and lateral band to band tunneling (L-BTBT) restrict the scaling of SOI-junctionless (JL) FETs. Therefore, in this paper, we investigate the scalability of the SOI-JLFETs by incorporating a ground plane (GP) inside a high-K buried oxide (BOX). Using calibrated 2-D simulations, it is demonstrated that a SOI-JLFET with the ground plane placed at a shallow depth within the high-K dielectric BOX not only assists in the efficient volume depletion of the channel but also results in a drastically reduced L-BTBT action. The efficient volume depletion, therefore, relaxes the constraints of ultra-thin silicon body for SOI-JLFET and circumvents the need of complex device architectures for achieving the same. Also, the depletion of the drain and source regions jointly results in a drastically reduced L-BTBT induced parasitic BJT action in the OFF-state and in the negative bias regime. The simultaneous suppression of both the leakage mechanisms results in an overall leakage current reduction leading to a significant ON-state to OFF-state current ratio (ION/IOFF) of 10 6 and 10 5 even at the scaled gate length of 10 nm and 7 nm, respectively. Additionally, a significant reduction in the draininduced barrier lowering and threshold voltage roll-off is observed in a GP-JLFET. The GP-JLFET also exhibits an appreciable I ON /I OFF ratio under the influence of process variations of doping and film thickness without any considerable degradation in the performance. Thus, the suppressed leakage mechanisms and short channel effects in the proposed device provide an incentive for realizing the SOI-JLFETs in the sub-10 nm regime for low power and low-leakage applications. INDEX TERMS Band-to-band tunneling (BTBT), Gate induced drain leakage (GIDL), Junctionless FET (JLFET), parasitic bipolar junction transistor (BJT), Drain induced barrier lowering (DIBL).

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In Memory Energy Application for Resistive Random Access Memory

Trotti

Oukassi

Molas

et al. 2021

Adv Elect Materials

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must be considered. This branch of research involves the so-called Moore than More's devices. [1] Some attempts to ease consumption rely on on-chip integration of nanoscale energy sources, [2,3] while others, notably in memory computing (IMU), [4] offer a revisited architecture where computation is decentralized. Other research groups proposed the integration of energy sources in close proximity of the memory, [5,6] or completely integrated within the memory architecture. [7] In this work, we explore a radically different concept, which lies on "dualbehavior" devices, able to store either information or energy, depending on the applied bias. Such capability would be greatly beneficial, allowing localized and high bandwidth energy supply to the processing unit (the memory or a dedicated arithmetic logic unit, ALU). The samples considered in our study indeed resemble ionic batteries at the nanoscale, providing ground to our inquiry of using these devices as energy sources, other than memory cells. Their operation relies on faradaic processes; therefore, the resulting energy density is expected to well exceed that of electrostatic capacitors, possibly being comparable to supercapacitors'. [8] The diameter of the devices under study can range between 1 and 100 µm, resulting in much smaller than the diameter of state-of-the-art planar supercapacitors (≈mm 2 ), [2] making such architecture more scalable and granular than any other state-of-the-art integrated power source. Energy storage is achievable when the device is, under a memory point of view, storing a logic 0, and could be accumulated during low logic operation activity for later use, for example, during the most power-hungry phases. These devices would also offer the advantage of placing the battery cell in close proximity to the target, meaning reduced IR drop and voltage undershoot, which develop in a typical inductive-impedance power delivery network (PDN). [9] A broad range of applications could be envisioned, each demanding different energy requirements, with widespread specifications. The most suitable target field should be selected taking into account the output voltage, energy, and power delivered by such RRAM-based batteries. In this work, we provide an outlook on some possible implementations, with some quantified ranges in terms of energy and instantaneous power requirements. Figure 1 reports the three main eligible domains: energy to memory, [10] energy to logic, [11] and neuromorphic computing. [12][13][14][15] This work explores the innovative concept of a hybrid dual-behavior device, based on emerging nonvolatile memory technology, for both data retention and energy storage. RRAM (resistive random access memory) is considered a major candidate as next-generation memory, thanks to its promising performances in terms of scalability and CMOS process compatibility. Its working mechanisms, based on faradaic processes, motivate the study on the feasibility of operating RRAM also as energy storage element. To evaluate the energy capability, various el...

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A Self-Tuning IoT Processor Using Leakage-Ratio Measurement for Energy-Optimal Operation

Cited by 39 publications

References 20 publications

Dynamic and Static Calibration of Ultra-Low-Voltage, Digital-Based Operational Transconductance Amplifiers

Dynamic and Static Calibration of Ultra-Low-Voltage, Digital-Based Operational Transconductance Amplifiers

Sub-10 nm Scalability of Junctionless FETs Using a Ground Plane in High-K BOX: A Simulation Study

In Memory Energy Application for Resistive Random Access Memory

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