A self-synchronized, crystal-less, 86&amp;#x00B5;W, dual-band impulse radio for ad-hoc wireless networks

Wang, Xiao Y.; Dokania, Rajeev; Zhuang, Yi; Godycki, Waclaw; Dorta-Quinones, Carlos I.; Lyons, Michael J.; Apsel, Alyssa

doi:10.1109/rfic.2011.5940613

Cited by 9 publications

(8 citation statements)

References 7 publications

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“…Earlier studies on analog complementary metal oxide semiconductor (CMOS) circuit implementations of pulse-coupled oscillators [13][14][15] have been published. These studies targeted communication device applications, and reported fast synchronization with low power consumption; however they are not related to large-scale networks mimicking brain architecture.…”

Section: Introductionmentioning

confidence: 99%

Parameterized digital hardware design of pulse-coupled phase oscillator networks

et al. 2015

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Section: Introductionmentioning

confidence: 99%

Parameterized digital hardware design of pulse-coupled phase oscillator networks

et al. 2015

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“…There has been earlier work about analog CMOS circuit implementation of pulse-coupled oscillators [11][12][13]. They targeted at applications of communication devices, and achieved fast synchronization with low power consumption.…”

Section: Introductionmentioning

confidence: 99%

Analog CMOS circuit implementation of a pulse-coupled phase oscillator system and observation of synchronization phenomena

Matsuzaka

Tohara

Nakada

et al. 2012

NOLTA

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Analog CMOS circuit implementation of a system of pulse-coupled phase oscillators is proposed. A CMOS circuit that achieves the dynamics of pulse-coupled oscillators has been designed and fabricated using a 0.25-μm CMOS technology. The proposed oscillator circuits with continuous-time operation interact with each other via a pulse at each firing time. Update of the oscillator state is achieved by integrating the phase sensitivity function with the pulse width time span. The phase sensitivity function is generated by the combination of binary functions, while the function consists of three-values {-1,0,1}. Introducing a zero-value span in the function leads to fast synchronization and robustness to parameter fluctuation due to LSI device mismatches, which facilitates VLSI implementation. Using the fabricated CMOS circuit, we have observed not only in-and anti-phase but also out-of-phase synchronization.

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“…Power consumption is dominated by the receiver, even with the duty cycling enabled. The limiting factor in this case appears to be the PLL cycle-to-cycle jitter, which is roughly a factor of two higher than an earlier iteration of the chip which we showed in [16].…”

Section: Power Consumptionmentioning

confidence: 59%

“…We wish to find the probability that this pulse is also in node2's timing bin. To do this, we first find the bin time offset, which is a sum of the PCO synchronization error and difference of the PLL locking errors of each node: (16) This can be broken down into deterministic offset and random jitter components as follows: (17) is the propagation jitter and is the relative-jitter of the PLL derived previously. We've lumped all offset sources into and all jitter sources into .…”

Section: ) Dll Offset and Jittermentioning

confidence: 99%

“…Such a paradigm is made possible through a unique clock distribution scheme utilizing a network of pulse coupled oscillators (PCO) modeled on the biological behavior of fireflies and described in [15]. A preliminary single transceiver design has been presented in [16] and [17] along with measurements showing that synchronization can be maintained between two transceivers. In this paper, we present a comprehensive analysis of our novel timing system and demonstrate that our scheme is capable of enabling robust packet-based communications between four transceivers through the implementation of a FPGA based baseband and medium access control (MAC) module.…”

Section: Introductionmentioning

confidence: 99%

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A Crystal-Less Self-Synchronized Bit-Level Duty-Cycled IR-UWB Transceiver System

Wang

Dokania

Apsel

2013

IEEE Trans. Circuits Syst. I

Self Cite

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A self-synchronized dual-band OOK IR-UWB transceiver system for short-range, low-data rate sensor networks is demonstrated. The transceiver system utilizes asynchronous non-coherent energy detection coupled with a novel pulse-coupled injection-locking scheme to synchronize transceivers throughout the network at nanosecond-scale precision. The pulse-coupled synchronization scheme compensates for intrinsic frequency variation so that all timing in the system can be derived from an integrated relaxation oscillator operating at a nominal frequency of 150 KHz. A low-jitter PLL and simple combinational logic is used for timing generation and control. The system is duty cycled between the expected arrival times of the sync and data pulses, allowing a demonstrated average RF duty cycle of less than 1% while being able to maintain synchronization for nearly 1 million cycles. Total measured system power consumption is 119 while actively communicating with 1200 bit packets. The transceiver was designed in a 90 nm IBM CMOS process and occupies 1.7 of active area.Index Terms-Impulse radio, low-power transceiver, pulse-coupled oscillator, sensor networks. 1549-8328 © 2013 IEEE

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A self-synchronized, crystal-less, 86µW, dual-band impulse radio for ad-hoc wireless networks

Cited by 9 publications

References 7 publications

Parameterized digital hardware design of pulse-coupled phase oscillator networks

Parameterized digital hardware design of pulse-coupled phase oscillator networks

Analog CMOS circuit implementation of a pulse-coupled phase oscillator system and observation of synchronization phenomena

A Crystal-Less Self-Synchronized Bit-Level Duty-Cycled IR-UWB Transceiver System

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