A self-organizing neural net chip

Mann, James R.; Lippmann, Richard P.; Berger, Bonnie; Raffel, J.I.

doi:10.1109/cicc.1988.20838

Cited by 21 publications

(9 citation statements)

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“…Bioinspired neuromorphic architectures are gaining interest for ultra low power computing [1]- [3], [12]. Although many of the current implementations rely on complementary metal-oxidesemiconductor (CMOS) devices [1], [3], [8]- [11], there has been a significant interest in incorporating emerging analog memory devices for more bio-inspired and energy-efficient computation [1], [2], [12]. However, a significant amount of research in developing ASICs for neural network acceleration has focused on supervised learning which requires large amounts of labeled data during training.…”

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confidence: 99%

“…In spite of its strengths, there has been limited research in developing neuromorphic hardware for implementing SOFM algorithms [8]- [12]. Many currently available hardware implementations of the SOFM algorithm utilize CMOS-only circuits that are penalized by the limitations of CMOS technology [8]- [11]. For example, CMOS memory devices store a single bit, requiring multiple memory devices per synapse to capture the analog nature of the incoming data.…”

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confidence: 99%

“…The use of separate memory modules to store weights [8]- [10] results in a lower memory bandwidth and higher energy consumption. Moreover, updating the weights serially [11] further increases computation time especially for high-dimensional datasets (i.e the COVID-19 chest x-ray images [14]). The higher computational time and energy requirements prevent real-time application in domains where rapid energy-efficient computation of results is crucial (e.g.…”

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confidence: 99%

“…Beyond computational challenges, some of these implementations often compromise key behaviors of the SOFM algorithm. The omission of learning rate decay [8], [9], [11], [12] may prevent the network from properly converging depending on the application and prevents lifelong continuous learning of the SOFM by over-training the network. Additionally, many implementations may rely on external circuitry for core behaviors costing computation time, circuit area, and power consumption [11].…”

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confidence: 99%

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NeuroSOFM: A Neuromorphic Self-Organizing Feature Map Heterogeneously Integrating RRAM and FeFET

Barve

Mayersky

Ford

et al. 2021

IEEE J. Explor. Solid-State Comput. Devices Circuits

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Many currently available hardware implementations of the unsupervised self-organizing feature map (SOFM) algorithm utilize CMOS-only circuits that often compromise key behaviors of the SOFM algorithm due to complexity. We propose a neuromorphic architecture harnessing the unique properties of FeFETs and gated-RRAM for in-memory computing to implement the SOFM algorithm. The FeFET-based synapse, organized in a novel circuit, is able to compute the input-weight Euclidean error in memory via the saturation drain current. The selfdecaying states of the gated-RRAM allow for a self-decaying neighborhood and learning rate implementation to allow for convergence and lifelong learning. This novel architecture is able to successfully cluster benchmarks (RGB colors and MNIST handwritten digits) and real-life datasets such as COVID-19 patient chest x-rays completely unsupervised. The architecture also demonstrates a significant amount of robustness to device variability and damaged neurons. Additionally, the proposed architecture is completely parallelized and provides a power efficient platform for implementing the SOFM algorithm.

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confidence: 99%

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confidence: 99%

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confidence: 99%

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confidence: 99%

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NeuroSOFM: A Neuromorphic Self-Organizing Feature Map Heterogeneously Integrating RRAM and FeFET

Barve

Mayersky

Ford

et al. 2021

IEEE J. Explor. Solid-State Comput. Devices Circuits

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“…Lincoln Lab 1987 [22] Naval Res. Lab 1988 [23] charge packets according to the desired programmed weights.…”

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confidence: 99%

Electronic implementation of neuromorphic systems

Raffel

Proceedings of the IEEE 1988 Custom Integrated Circuits Conference

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The electronic implementation of neuromorphic systen= requires technologies well matched to the functions of storage and the computation of sums of products. Additional requirements are low power, high fan-out capability and high density interconnect. Massive parallelism and redundancy mitigate the accuracy limitations of analog circuits and force reconsiderat ion of analog and analog-digital components for network realization. Adaptive neuroinorphic networks have the potential for self-organization a n d Icarning in speech and image understanding systems requiring minimal human intervention.

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Self-Organization Neural Networks

Sheu¹,

Choi²

1995

Neural Information Processing and VLSI

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A self-organizing neural net chip

Cited by 21 publications

References 0 publications

NeuroSOFM: A Neuromorphic Self-Organizing Feature Map Heterogeneously Integrating RRAM and FeFET

NeuroSOFM: A Neuromorphic Self-Organizing Feature Map Heterogeneously Integrating RRAM and FeFET

Electronic implementation of neuromorphic systems

Self-Organization Neural Networks

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