A self-diagnostic BIST memory design scheme

Mo, Chin Tsung; Lee, Chung Len; Wu, Wen Ching

doi:10.1109/mtdt.1994.397205

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Cited by 8 publications

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“…In [9] an efficient BIST scheme for naked memories is described for which fault diagnosis comes for free. Still another BIST scheme with self diagnostic capabilities are described in [8]. A memory BIST that is based on error detecting codes is described in [6].…”

Section: Introductionmentioning

confidence: 99%

BIST‐Based Fault Diagnosis in the Presence of Embedded Memories

Savir

2000

VLSI Design

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An efficient method is described for using fault simulation as a solution to the diagnostic problem created by the presence of embedded memories in BIST designs. The simulation is event-table-driven. Special techniques are described to cope with the faults in the Prelogic, Postlogic, and the logic embedding the memory control or address inputs. It is presumed that the memory itself has been previously tested, using automatic test pattern generation (ATPG) techniques via the correspondence inputs, and has been found to be fault-free.

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Section: Introductionmentioning

confidence: 99%