A self-calibration technique for fast-switching frequency-hopped UWB synthesis

Ojani, Amin; Mesgarzadeh, Behzad; Alvandpour, Atila

doi:10.1109/mixdes.2014.6872176

Cited by 1 publication

(5 citation statements)

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“…The second fast hopping DLL-based architecture employs the concept of T/H [7]. During a start-up phase, the lock voltages of the DLL for the three sub-bands of WiMedia UWB bandgroup 1, are sampled and stored across three corresponding capacitors.…”

Section: Resultsmentioning

confidence: 99%

“…The synthesizer architecture of [7] exhibits the potential for improving the hopping speed, phase noise, and harmonic spurs of the synthesizer at the same time. Implementing this architecture on silicon and verifying the achievable performance from the measurement results can also be considered as a valuable future work.…”

Section: Future Workmentioning

confidence: 99%

“…Chapter 9 is based on Paper 7 [7] and develops another fast hopping DLL-based architecture for UWB frequency synthesis. The introduced architecture employs the concept of track-and-hold (T/H) to sample the lock control voltages of the WiMedia UWB channels and store them across the corresponding capacitors during a start-up phase.…”

Section: Introductionmentioning

confidence: 99%

“…In recirculating DLL-based approach [54]- [61], where the multiplied clock is generated by a similar mechanism as in a ring VCO-based PLL, the harmonic SCR is directly defined by the output frequency and the SPE of the locked-loop [60], [61]. In edge-combining DLL-based synthesizers [1]- [7] , [35], [36], [62]- [67], on the other hand, the carrier is generated by combining the equally-spaced DLL edges, and hence, misalignments of those edges result in periodic jitter and raise the reference harmonic spurs at the output spectrum of the synthesizer. These harmonic spurs can potentially downconvert the out-of-band interferers into the desired band.…”

Section: Introductionmentioning

confidence: 99%

“…This chapter covers [7] to present a fast switching DLL-based technique for frequency synthesis in bandgroup 1 of WiMedia UWB communication. The proposed architecture employs the concept of T/H to sample the lock control voltages of the three sub-bands and store them across three capacitors during a start-up phase.…”

Section: Introductionmentioning

confidence: 99%

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Analysis and Design of DLL-Based Frequency Synthesizers for Ultra-Wideband Communication

Ojani¹

2015

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Sweden Cover image:The cover image illustrates a sine-shaped "wordle" of the thesis.Printed by LiU-Tryck, Linköping University Linköping, Sweden, 2014 iii AbstractEver increasing demand for high speed transmission of large data between the electronic devices within a wireless personal area network has been motivating the development of the appropriate wireless standards. Ultra-wideband (UWB) communication employs the unlicensed frequency spectrum of 3.1 -10.6 GHz and utilizes a low average transmit power to offer the potential for high data rates in short range wireless links. WiMedia specification for UWB employs a frequency hopping scheme which requires a very fast hopping speed of 9.47 ns. Also, the strong interferers from the coexisting wireless technologies put stringent requirements on synthesizer's sideband spurs. Satisfying such challenging requirements using conventional frequency synthesis approaches is impractical and demands for exploration, analysis and design of new synthesizer architectures.Essential characteristics of a delay-locked loop (DLL), such as its first-order loop stability, relatively wide loop bandwidth, and low jitter accumulation, make DLL-based architectures attractive candidates for fast switching and low phase noise frequency synthesis applications. However, as an edge-combiner (EC) is required to produce different frequencies than that of the reference clock, any misalignment in equallyspaced DLL output edges will generate an erroneous periodicity, resulting in reference sideband spurs at the output spectrum of the frequency synthesizer.This thesis investigates the opportunities and challenges of employing DLL-based architectures to synthesize carrier frequencies for wireless applications, specifically UWB communication. The dissertation has contributed to two aspects of the topic; mathematical modeling and analysis, as well as circuit design and implementation.A comprehensive behavioral model of the harmonic spur levels in edge-combining DLL-based frequency synthesizers is developed which includes the effects of the stagedelay mismatch, the static phase error of the locked-loop, and the duty cycle distortion iv of the reference clock. Utilizing Fourier series representation of the DLL output phases, an analytical expression for synthesizer's spur levels is derived. Applying Taylor series approximations and moment methods to the analytical formula, closed-form expressions are obtained for the probability density function and mean value of the harmonic spur magnitudes. Finally, a Monte Carlo-free spur-aware design flow is introduced which significantly accelerates the iterative design procedure of the synthesizer. Accuracy and robustness of the prediction method against wide-range values of the non-idealities are investigated and verified through Monte Carlo simulations of the synthesizer's behavioral and transistor-level model in a 65-nm CMOS process.Three DLL-based architectures are developed and designed. In the first architecture, fast hopping frequency synthesis is achieve...

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Section: Resultsmentioning

confidence: 99%

Section: Future Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A self-calibration technique for fast-switching frequency-hopped UWB synthesis

Cited by 1 publication

References 8 publications

Analysis and Design of DLL-Based Frequency Synthesizers for Ultra-Wideband Communication

Analysis and Design of DLL-Based Frequency Synthesizers for Ultra-Wideband Communication

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