A self‐calibrated delay‐locked loop with low static phase error

Abstract

SUMMARYIn conventional delay-locked loop circuits, the charge and discharge of the charge pump result in mismatched current reflecting the size of the static phase error. The static phase error between feedback clock and reference clock is likely to be within tens or hundreds of picoseconds (ps). We thus propose an approach using digital calibration methods to reduce the charge pump current mismatch by means of the setup time of the D-type flip flop. The setup time of D-type flip flop is determined and duplicated to detect the phase error between the reference clock and feedback clock. It results in a very small static phase error between the reference clock and feedback clock. This paper used a 0.18 μm CMOS process design, with a reference frequency of 700~900 MHz. The active area is 0.031 mm 2 , and the phase error after correction is less than 5 ps.

A single‐bit continuous‐time delta‐sigma modulator using clock‐jitter and inter‐symbol‐interference suppression technique

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A 6-Locking Cycles All-Digital Duty Cycle Corrector with Synchronous Input Clock

“…To control circuit triggering under high-frequency operation, the accuracy of the frequency, phase, and pulse width of the clock signal is important for circuit applications. However, the Phase Locked Loop (PLL) [1][2][3] or Delay Locked Loop (DLL) [4][5][6], can only correct the signal frequency and phase, so the Duty Cycle Corrector (DCC) [7][8][9][10][11][12][13][14][15][16][17][18][19][20] was developed to correct the output duty cycle. The duty cycle of a clock plays a very important role in many circuit operations.…”

Frequency‐domain behavioural noise analysis of analogue phase‐locked loops

“…This paper is confined to multiplier‐type PDs. The reason is that the sequential‐type PDs have complex time‐dependent responses which are triggered at signal transitions that cannot be easily modelled with common non‐linear functions plus LTI responses [4, 18, 30].…”