A 6-Locking Cycles All-Digital Duty Cycle Corrector with Synchronous Input Clock

Abstract

This paper proposes an all-digital duty cycle corrector with synchronous fast locking, and adopts a new quantization method to effectively produce a phase of 180 degrees or half delay of the input clock. By taking two adjacent rising edges input to two delay lines, the total delay time of the delay line is twice the other delay line. This circuit uses a 0.18 μm CMOS process, and the overall chip area is 0.0613 mm2, while the input clock frequency is 500 MHz to 1000 MHz, and the acceptable input clock duty cycle range is 20% to 80%. Measurement results show that the output clock duty cycle is 50% ± 2.5% at a supply voltage of 1.8 V operating at 1000 MHz, the power consumed is 10.1 mW, with peak-to-peak jitter of 9.89 ps.

Design and Analysis of Asynchronous Sampling Duty Cycle Corrector

“…Moreover, their detection accuracies are severely affected (and degraded) by any offset voltages in duty cycle detection circuits [14,15], which is not a desirable factor in advanced CMOS technologies with higher device mismatches and offsets. A time-to-digital-conversion (TDC) based duty cycle detector is utilized in [16,17] to resolve the accuracy and variation issues by utilizing fine-resolution TDC circuits. However, the technique requires the use of more than two TDCs, which significantly reduces area efficiency and increases power consumption.…”