A self-aligned retrograde twin-well structure with buried p/sup +/-layer

Odanaka, S.; Yabu, T.; Shimizu, Naoji; Umimoto, H.; Ohzone, T.

doi:10.1109/55.31746

Cited by 5 publications

(3 citation statements)

References 9 publications

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“…However, the high to low profile does not require any special sputtering or ion-implant step (as is required for halo/retrograde doping) and hence, significantly reduces the process complexity and cost [18].…”

Section: Doping Profile Considerationsmentioning

confidence: 99%

Device optimization for ultra-low power digital sub-threshold operation

Paul

Raychowdhury

Roy

2004

Proceedings of the 2004 International Symposium on Low Power Electronics and Design

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Digital circuits operated in the sub-threshold region (supply voltage less than the transistor threshold voltage) can have orders of magnitude power advantage over standard CMOS circuits for applications requiring ultra-low power and medium frequency of operation. It is possible to implement sub-threshold logic circuits using the standard transistors that are designed primarily for ultra high performance super-threshold logic design. However, a Si MOSFET so optimized for performance in the super-threshold regime is not the best device to use in the sub-threshold domain. In this paper, we propose device designs apt for sub-threshold operation. Results show that the optimized device improves the delay and power delay product (PDP) of an inverter chain by 44% and 51%, respectively, over the normal super-threshold device operated in the sub-threshold region.

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Section: Doping Profile Considerationsmentioning

confidence: 99%

Device optimization for ultra-low power digital sub-threshold operation

Paul

Raychowdhury

Roy

2004

Proceedings of the 2004 International Symposium on Low Power Electronics and Design

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“…[1][2][3][4][5][6][7][8][9][10] Many device characteristics, such as hot carrier generation, channel mobility, punchthrough voltage, junction capacitance, latchup susceptibility, and soft error immunity can be improved and/or optimized by multiple-chain high-energy ion implantations. [8][9][10] In the deep submicrometer regime, a retrograde well with a buried layer formed by a megaelectronvolt ion implantation that replaces the use of an epi layer has been used to obtain a latchup-free condition.…”

mentioning

confidence: 99%

“…A retrograde well has been extensively utilized in the very large scale integrated ͑VLSI͒ circuits because of its advantages of chip size reduction, low thermal budget, process simplification, and improvements of surface topography and device performance. [1][2][3][4][5][6][7][8][9][10] Many device characteristics, such as hot carrier generation, channel mobility, punchthrough voltage, junction capacitance, latchup susceptibility, and soft error immunity can be improved and/or optimized by multiple-chain high-energy ion implantations. [8][9][10] In the deep submicrometer regime, a retrograde well with a buried layer formed by a megaelectronvolt ion implantation that replaces the use of an epi layer has been used to obtain a latchup-free condition.…”

mentioning

confidence: 99%

Implantation Induced Defects in the Retrograde Well with a Buried Layer

Hsu

Liang

Chen

2002

J. Electrochem. Soc.

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This work investigates the implantation induced extended defects in the retrograde p-and n-well with/without a buried layer after postimplantation thermal annealing at 950°C in N 2 ambient. A preferential etchant of CrO 3 /HF mixed solution was used to delineate the defects induced by high-energy ion implantation. It is found that the extended defects elongated to the top surface of the retrograde well with a buried layer, which was implanted with high-energy boron ion at 1500 keV to a dose of 3 ϫ 10 13 cm Ϫ2 , resulting in the etching pits of extended defects at a density of about 10 5 cm Ϫ2 .

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Chip Reliability

El-Kareh¹,

Hutter²

2015

Silicon Analog Components

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A self-aligned retrograde twin-well structure with buried p/sup +/-layer

Cited by 5 publications

References 9 publications

Device optimization for ultra-low power digital sub-threshold operation

Device optimization for ultra-low power digital sub-threshold operation

Implantation Induced Defects in the Retrograde Well with a Buried Layer

Chip Reliability

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