2000
DOI: 10.1016/s0167-9317(99)00264-6
|View full text |Cite
|
Sign up to set email alerts
|

A selective CMP process for stacked low-k CVD oxide films

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1
1
1

Citation Types

0
12
0

Year Published

2002
2002
2017
2017

Publication Types

Select...
5
3

Relationship

0
8

Authors

Journals

citations
Cited by 27 publications
(12 citation statements)
references
References 0 publications
0
12
0
Order By: Relevance
“…Hartmannsgruber et al 12 studied the CMP removal selectivity between the low-k Flowfill layer and PECVD oxide layer, reporting an increasing low-k removal rate and a decreasing or nearconstant PECVD oxide removal rate with increasing additive concentration in the slurry. Hara et al 13,14 studied CMP of FLARE and fluorinated carbon with fumed SiO 2 , MnO 2 , Mn 2 O 3 , and CeO 2 slurries.…”
Section: Literature Reviewmentioning
confidence: 99%
“…Hartmannsgruber et al 12 studied the CMP removal selectivity between the low-k Flowfill layer and PECVD oxide layer, reporting an increasing low-k removal rate and a decreasing or nearconstant PECVD oxide removal rate with increasing additive concentration in the slurry. Hara et al 13,14 studied CMP of FLARE and fluorinated carbon with fumed SiO 2 , MnO 2 , Mn 2 O 3 , and CeO 2 slurries.…”
Section: Literature Reviewmentioning
confidence: 99%
“…In microelectronic industry many researchers have been actively working toward finding threshold values of hardness and elastic modulus that can provide Cu/low-k system the ability to withstand CMP and wire bonding processes [28][29][30]. Researchers at Motorola [43] have concluded that passing the CMP process of low-k material is not a simple factor of modulus, hardness, adhesion or toughness, but a combination of all of these properties.…”
Section: Mechanical Characterization Of Low-k Structures By Using Nanmentioning
confidence: 99%
“…Chemical mechanical polishing (CMP) is a key enabler for global and local planarization and has been intensively investigated from various angles [3,4]. According to the standard dual-damascene interconnect process for copper, the barrier layer (Ta/TaN, Mo, Co, Ru, and their alloy) is deposited onto the dielectric prior to the electroplating of copper [5,6].…”
Section: Introductionmentioning
confidence: 99%