The effects of chemical mechanical planarization ͑CMP͒ process parameters and consumables on the polish rate and defects generated in various low-k materials with k values ranging from 2.2 to 3.0 were studied in detail. The process consumables and conditions evaluated include slurry material ͑alumina and silica͒, pad type ͑soft and hard͒, polish pressure, and polish time. Atomic force microscopy ͑AFM͒ images and roughness numbers were used to evaluate the post-CMP defect generation under various process conditions and revealed nano/microscratches, pits, voids, and film delamination. For a given material, the removal rate increased with increasing pressure. The dependence of defects on pressure appeared highly driven by the slurry material, pad type, and low-k material properties. Defects increased with increasing pad hardness and decreasing k values. The increasing defects with decreasing k value can be attributed to the lower elastic modulus observed with low-k materials. Removal rates exhibited both a decrease and an increase in conjunction with polish time, depending on the type of low-k material used. AFM analysis showed an improvement in global surface roughness with increasing polish time; however, an increase in localized defects such as pits was also observed. Fourier transform infrared and X-ray photoelectron spectroscopy analyses showed no change in film chemistry under the conditions studied here.With advancements in ultralarge-scale integration, integrated microelectronic device dimensions are continually being scaled down. At present, manufacturers are running 0.11 m technology in their production lines, which increases the number of dies per wafer and reduces manufacturing costs. In addition, higher device speed requirements have forced the industry to include material changes in the device interconnection array. For example, in an attempt to reduce the resistance-capacitance time delay, manufacturers have moved toward a copper damascene process, with copper replacing aluminum and low-k dielectric materials replacing SiO 2 .Chemical mechanical planarization ͑CMP͒ is an important step in the copper damascene process. Copper deposited in the patterned dielectric trenches is planarized by CMP. The primary objective of the Cu-CMP process is to planarize and remove excess copper and the barrier layer. During this process, the underlying dielectric material is exposed. With industry shifts toward ultra low-k materials, very low k values can usually be achieved by using porous/organic materials, which also exhibit low hardness and modulus. However, these relatively weak materials cannot withstand the rigorous CMP process. Additionally, low-k films are less moisture resistant than conventional oxides produced by chemical vapor deposition ͑CVD͒; thus, extended exposure to CMP slurries and the environment affects their properties.Numerous low-k materials are being investigated. The compatibility of these materials with the CMP process is a significant factor in determining the appropriate low-k material to us...
The adsorption-desorption of various cations at the silica-water interface is discussed in terms of electrical double layer and surface complexation models. Some experimentally determined surface equilibria constants from the literature are tabulated for Fe, Cu, and Mg. The adsorption phenomena of those cations onto silica gel is described using the stability calculation (STABCAL) computer program based on the suggested models.A chemical oxide (silica) is grown on the silicon surface during the SCI and/or SC2 processes. Adsorption of Fe, Cu, and Mg onto this chemical oxide is studied as a function of pH and compared to the modeling results. In general, there is a qualitative correlation between the experimental and modeling data, which can be used as a basis to develop a quantitative model for cation adsorption-desorption on the wafer surface.
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