A Secure Content Delivery System Based on a Partially Reconfigurable FPGA

Hori, Yohei; Yokoyama, Haruki; Sakane, Hitoshi; Toda, Kenji

doi:10.1093/ietisy/e91-d.5.1398

Cited by 8 publications

(6 citation statements)

References 18 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Partial reconfiguration technology has attracted many researchers for filling the gap between hardware and software for algorithm implementation. Recently, in computer security applications, partial reconfiguration is applied in AES (Advanced Encryption Standard) algorithm implementation [7]. It also had been used to accelerate video processing in driver assistance system [3].…”

Section: Related Workmentioning

confidence: 99%

Adaptive Flux Calculation Scheme in Advection Term Computation Using Partial Reconfiguration

Talip

Akamine

Hatto

et al. 2013

IJNC

View full text Add to dashboard Cite

In aerospace industry, computational fluid dynamics (CFD) is used as a common design tool. Fast Aerodynamics Routines (FaSTAR) is one of the most recent CFD software package, convenient for users with various solvers and automatic generation of grid data. The problem of FaSTAR is hard to be executed in parallel machines because of its irregular and unpredictable data structure. Exploiting reconfigurable hardware with their advantages to make up for the inadequacy of the existing high performance computers had gradually become the solutions and trends. However, a single FPGA is not enough for the FaSTAR package because the whole module is very large. Instead of using a large number of chips, partially reconfigurable hardware available in recent FPGAs is explored for this application. Advection term computation module in FaSTAR is chosen as a target subroutine. We proposed a reconfigurable flux calculation scheme using partial reconfiguration technique to save hardware resources to fit in a single FPGA. We developed flux computational module and three flux calculation schemes are implemented as reconfigurable modules. This implementation has advantages of up to 42% resource saving and enhancing the configuration speed by 6.28 times. Performance evaluation also shows that 2.65 times acceleration is achieved compared to Intel Core 2 Duo at 2.4GHz.

show abstract

Section: Related Workmentioning

confidence: 99%

Adaptive Flux Calculation Scheme in Advection Term Computation Using Partial Reconfiguration

Talip

Akamine

Hatto

et al. 2013

IJNC

View full text Add to dashboard Cite

show abstract

“…Therefore, partial reconfiguration technology has attracted many researchers in this field. Recently, this technology was applied to information and communication system security [14]. In computer security applications field, partial reconfiguration is applied in AES algorithm implementation [15].…”

Section: Related Workmentioning

confidence: 99%

Partial Reconfiguration of Flux Limiter Functions in MUSCL Scheme Using FPGA

Talip

Akamine

Osana

et al. 2012

IEICE Trans. Inf. & Syst.

View full text Add to dashboard Cite

SUMMARYComputational Fluid Dynamics (CFD) is used as a common design tool in the aerospace industry. UPACS, a package for CFD, is convenient for users, since a customized simulator can be built just by selecting desired functions. The problem is its computation speed, which is difficult to enhance by using the clusters due to its complex memory access patterns. As an economical solution, accelerators using FPGAs are hopeful candidate. However, the total scale of UPACS is too large to be implemented on small numbers of FPGAs. For cost efficient implementation, partial reconfiguration which dynamically loads only required functions is proposed in this paper. Here, the MUSCL scheme, which is used frequently in UPACS, is selected as a target. Partial reconfiguration is applied to the flux limiter functions (FLF) in MUSCL. Four FLFs are implemented for Turbulence MUSCL (TMUSCL) and eight FLFs are for Convection MUSCL (CMUSCL). All FLFs are developed independently and separated from the top MUSCL module. At start-up, only required FLFs are selected and deployed in the system without interfering the other modules. This implementation has successfully reduced the resource utilization by 44% to 63%. Total power consumption also reduced by 33%. Configuration speed is improved by 34-times faster as compared to full reconfiguration method. All implemented functions achieved at least 17 times speed-up performance compared with the software implementation. key words: computational fluid dynamics (CFD), field programmable gate array (FPGA), scientific computations, reconfigurable hardware, partial reconfiguration

show abstract

“…Thus, by using DPR, the functionality of the system is dynamically altered by replacing hardware modules according to, e.g., user-requested content, performance requirements, and environmental changes. Many applications of DPR have been reported, including content distribution security [1], image processing [2], fault-tolerant systems [3], and software-defined radio [4].…”

Section: Introductionmentioning

confidence: 99%

Bitstream Protection in Dynamic Partial Reconfiguration Systems Using Authenticated Encryption

Hori

Katashita

Sakane

et al. 2013

IEICE Trans. Inf. & Syst.

View full text Add to dashboard Cite

SUMMARYProtecting the confidentiality and integrity of a configuration bitstream is essential for the dynamic partial reconfiguration (DPR) of field-programmable gate arrays (FPGAs). This is because erroneous or falsified bitstreams can cause fatal damage to FPGAs. In this paper, we present a high-speed and area-efficient bitstream protection scheme for DPR systems using the Advanced Encryption Standard with Galois/ Counter Mode (AES-GCM), which is an authenticated encryption algorithm. Unlike many previous studies, our bitstream protection scheme also provides a mechanism for error recovery and tamper resistance against configuration block deletion, insertion, and disorder. The implementation and evaluation results show that our DPR scheme achieves a higher performance, in terms of speed and area, than previous methods. key words: dynamic partial reconfiguration (DPR), field-programmable gate array (FPGA), Advanced Encryption Standard (AES), Galois/Counter Mode (GCM), authenticated encryption

show abstract

A Secure Content Delivery System Based on a Partially Reconfigurable FPGA

Cited by 8 publications

References 18 publications

Adaptive Flux Calculation Scheme in Advection Term Computation Using Partial Reconfiguration

Adaptive Flux Calculation Scheme in Advection Term Computation Using Partial Reconfiguration

Partial Reconfiguration of Flux Limiter Functions in MUSCL Scheme Using FPGA

Bitstream Protection in Dynamic Partial Reconfiguration Systems Using Authenticated Encryption

Contact Info

Product

Resources

About