A search-based bump-and-refit approach to incremental routing for ECO applications in FPGAs

Proceedings of the 41st Annual Design Automation Conference

Suthar

2004

Self Cite

We present novel and efficient methods for on-line testing in FPGAs. The testing approach uses a ROving TEster (ROTE), which has provable diagnosabilities and is also faster than prior FPGA testing methods. We present 1-and 2-diagnosable built-in self-tester (BISTer) designs that make up the ROTE, and that avoid expensive adaptive diagnosis. To the best of our knowledge, this is the first time that a BISTer design with diagnosability greater than one has been developed for FPGAs. We also develop functional testing methods that test PLBs in only two circuit functions that will be mapped to them (as opposed to testing PLBs in all their operational modes) as the ROTE moves across a functioning FPGA. Simulation results show that our 1-diagnosable BISTer and our functional testing technique leads to significantly more accurate (98% (90.5%) fault coverage at a fault/defect density of 10% (25%)) and faster test-and-diagnosis of FPGAs than achieved by previous work. In general, it is expected that ROTE will achieve high fault coverages at fault/defect densities of up to 25% using our 1-diagnosable BISTer and up to 33% using our 2-diagnosable BISTer. Our methods should thus prove useful for testing current very deep submicron FPGAs as well as future nano-CMOS and molecular nanotechnology FPGAs in which defect densities are expected to be in the 10% range.

“…2. Perform incremental re-routing (e.g., [4,5]) to extend/reroute each interconnect going originally to u to now connect to v for each adjacent¨u v pair in a reconfiguration path. …”

Section: The Big Picture -Roving Tester and Fault Reconfigurationmentioning

confidence: 99%

Efficient on-line testing of FPGAs with provable diagnosabilities

Verma

Proceedings of the 41st Annual Design Automation Conference

Suthar

2004

Self Cite

“…Past work tackling the incremental routing problem include [1,2,3,4,5,10]. In [1], re-routing is done in a standard singlenet routing mode in the available routing space without disturbing existing net routes; we term this incremental routing approach Standard (Std).…”

Section: Introductionmentioning

confidence: 99%

“…The main disadvantage of a R&R scheme is that the routing is no longer truly incremental, as there is no limit to the extent of ripups of existing nets, and there is little control on the quality of their re-routes. An incremental routing algorithm for FPGAs that uses a bump-and-refit (B&R) approach which routes the new nets by "bumping" less critical existing nets in a controlled manner and without changing their topologies was proposed in [4] and was extended for ECO routing and for FPGAs with complex switchboxes in [3]. Finally, the algorithm presented in [5] uses a depth-first search (DFS) controlled B&R process to find good-quality incremental routing solutions using a gridless framework for VLSI circuits that require variable width and variable spacing on interconnects.…”

Section: Introductionmentioning

confidence: 99%

Efficient Timing-Driven Incremental Routing for VLSI Circuits Using DFS and Localized Slack-Satisfaction Computations

Proceedings of the Design Automation &Amp; Test in Europe Conference

Arslan

2006

Abstract:In current very deep submicron (VDSM) circuits, incremental routing is crucial to incorporating engineering change orders (ECOs) late in the design cycle. In this paper, we address the important incremental routing objective of satisfying timing constraints in high-speed designs while minimizing wirelength, vias and routing layers. We develop an effective timing-driven (TD) incremental routing algorithm TIDE for ASIC circuits that addresses the dual goals of time-efficiency, and slack satisfaction coupled with effective optimizations. There are three main novelties in our approach: (i) a technique for locally determining slack satisfaction of the entire routing tree when either a new pin is added to the tree or an interconnect in it is re-routed-this technique is used in both the global and detailed routing phases; (ii) an interval-intersection and tree-truncation algorithm, used in global routing, for quickly determining a near-minimumlength slack-satisfying interconnection of a pin to a partial routing tree; (iii) a depth-first-search process, used in detailed routing, that allows new nets to bump and re-route existing nets in a controlled manner in order to obtain better optimized designs. Experimental results show that within the constraint of routing all nets in only two metal layers, TIDE succeeds in routing more than 94% of ECO-generated nets, and also that its failure rate is 7 and 6.7 times less than that of the TD versions of previous incremental routers Standard (Std) and Ripup&Reroute (R&R), respectively. It is also able to route nets with very little (3.4%) slack violations, while the other two methods have appreciable slack violations (16-19%). TIDE is about 2 times slower than the simple TD-Std method, but more than 3 times faster than TD-R&R.

“…The B&R approach along with a depth-first search (DFS) algorithm was proposed originally in [1,2] for the purpose of incremental routing. A similar B&R approach can be used for complete detailed routing, since the routing of the current net in the presence of the previously routed nets is qualitatively an incre-£ This work was supported in part by NSF grant CCR-0204097.…”

Section: Introductionmentioning

confidence: 99%

“…In the former, it may need to be applied to 1-10% of the nets, while in the latter, it is applied to almost 100% of the nets. A straightforward application of the DFS B&R incremental algorithm of [1,2] to the complete routing problem results in slow to extremely slow solution times on a set of medium to large VPR circuits. To alleviate this problem, we develop here a suite of optimality-preserving speedup methods that results in speedups of several orders of magnitude.…”

Section: Introductionmentioning

confidence: 99%

ROAD: an order-impervious optimal detailed router for FPGAs

Arslan

Proceedings 21st International Conference on Computer Design

: It is well known that the solution quality of the detailed routing phase is heavily influenced by the order in which nets are routed. To alleviate this situation a number of routing strategies have been developed that ripup and reroute (R&R) previously-routed nets that "block" the current net. In the R&R approach, there is not a significant amount of control over the solution quality (e.g., length, delay) for the ripped-up nets. In this paper we propose a detailed router ROAD (bump&Refit based OptimAl Detailed router) that explores the solution space using an approach called bump-and-refit (B&R) in which the global routes of prior-routed nets are not changed but their track assignments are systematically altered in order to make space for the current net being routed. B&R thus does not have the above drawback of R&R. We start with an initial depth-first search method for this purpose that is optimal in finding a detailed routing solution with the minimum number of tracks irrespective of the net routing order. We then develop various optimality-preserving speedup methods including search space pruning based on clique detection and learning about and remembering unsuccessful search spaces, and second-level or lookahead transition costs. The combination of these methods results in an average speedup of 604 for small to medium VPR circuits and an extrapolated speedup of more than 5763 for larger circuits. Furthermore, comparison of ROAD run times to that of VPR's estimated detailed routing phase show that we are almost two times faster than VPR. This is noteworthy because an optimal detailed router is able to obtain solutions in reasonable times which are also faster than those of a non-optimal (though effective) router.