A Scheme to Improve the Stability and Accuracy of Power Hardware-in-the-Loop Simulation

Abstract

Power hardware-in-the-loop (PHIL) is a state-ofthe-art simulation technique that combines real-time digital simulation and hardware experiments into a closed-loop testing environment. The transportation delay or communication latency impacts the stability and accuracy of PHIL simulations. In this paper, for the purpose of synchronizing the PHIL output signal and promoting both the stability and accuracy of PHIL simulation, a hybrid compensation scheme is proposed to compensate for the time delay in the PHIL configuration. A model-based compensator is implemented to shift the time delay out of the PHIL closed-loop to enhance PHIL stability. A time delay compensation model and its equivalent inverse model are employed in the PHIL closed-loop to compensate for the time delay. A phase lead compensator and digital linear-phase frequency sampling filter (FSF) are candidate compensation models to compensate for the time delay and reshape the phase curve on a harmonic-by-harmonic basis. Simulations are made to validate the effectiveness of the compensation scheme.Index Terms-Power hardware-in-the-loop (PHIL), time delay compensation, model-based compensator, stability and accuracy.

Interface Compensation for More Accurate Power Transfer and Signal Synchronization within Power Hardware-in-the-Loop Simulation

“…exists a power factor angle tracking error due to the phase lag of the power amplifier output filter in (17). Because the compensation method proposed in this paper maintains the unity gain of the power amplifier and takes both the loop time delay and the phase lag of the power amplifier output filter into consideration, as shown in case 4), the PHIL system compensated by the proposed method presents remarkably improved power signal tracking capabilities regarding the RMS voltage, power factor angle, and the active power and reactive power.…”

“…As reported in our previous work [17], the phase lag within the PHIL setup is compensated by the frequency sampling filter (FSF)-based compensation scheme on a harmonic-byharmonic basis. The FSF is implemented as a non-recursive finite impulse response (FIR) filter, of which the linear phase and steep cut-off amplitude characteristics enable the selective update of the signal phase and amplitude characteristics over a wide range of frequencies [19].…”

“…According to the frequency response of the FSF in [17], the comb filter presents periodically spaced notches and the complex resonators present periodically spaced sharp peaks at the fundamental and harmonic frequencies. The FSF filter implemented as a comb filter in series with k-th order complex resonator is equivalent to a band-pass filter centred at the resonant frequency kw 0 and the scaling factor 1 N is implemented at the output of each single resonator to mitigate the overflow error and maintain the unity gain of the FSF filter.…”

“…5 presents the block diagram of the FSF-based phase lag compensation filters. To compensate for the phase lags of the compensated filter in (17) and the loop time delay, an additional phase shift φ s k is implemented at the output of the resonator with resonant frequency kw 0 . The FSF implemented with additional phase shift can be expressed as:…”

“…2) The non-zero phase shift introduced by the power amplifier output filter presents the same effects as the loop phase lag that results from the time delay introduced by multiple stages within the PHIL closed-loop [16], on reducing the system stability margin, deteriorating the power signal synchronization, and degrading the transparency of power transfer between the DRTS and the HUT [11], [16], [17].…”