A Scheduling Discipline for Latency and Bandwidth Guarantees in Asynchronous Network-on-Chip

Bjerregaard, Tobias; Sparsø, Jens

doi:10.1109/async.2005.7

Cited by 80 publications

(74 citation statements)

References 18 publications

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“…Therefore, the lossless networks in which flits are never dropped is an idealistic assumption. Practically each link must also implement back pressure flow control, ensuring that a flit can only be transmitted on a channel if the receiving end has free buffer space [42]. This introduces an extra layer of admission control to the trans-receiver logic or the communicating node.…”

Section: Elastic Channels and Buffersmentioning

confidence: 99%

Realization of Efficient High Throughput Buffering Policies for Network on Chip Router

Nazir¹,

Mir²

2016

IJCNIS

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Abstract-The communication between processing elements is suffering challenges due to power, area and latency. Temporary flit storage during communication consumes the maximum power of the whole power consumption of the chip. The majority of current NoCs consume a high amount of power and area for router buffers only. Removing buffers and virtual channels (VCs) significantly simplifies router design and reduces the power dissipation by a considerable amount. The buffering scheme used in virtual channeling in a networkon-chip based router plays a significant role in determining the performance of the whole network-onchip based mesh. Elastic buffer (EB) flow control is a simple control logic in the channels to use pipeline flipflops (FFs) as storage locations. With the use of elastic buffers, input buffers are no longer required hence leading to a simplified router design. In this paper properties of buffers are studied with a test microarchitecture router for several packet injection rates given at an input port. The prime contribution of this article is the evaluation of various forms of the elastic buffers for throughput, FPGA resource utilization, average power consumed, and the maximum speed offered. The article also gives a comparison with some available buffering policies against throughput. The paper presents the synthesis and implementation on FPGA platforms. The work will help NoC designers in suitable simple router implementation for their FPGA design. The implementation targets Virtex5 FPGA and Stratix III device family.

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Section: Elastic Channels and Buffersmentioning

confidence: 99%

Realization of Efficient High Throughput Buffering Policies for Network on Chip Router

Nazir¹,

Mir²

2016

IJCNIS

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“…From the architectural point of view, a complete scheme is presented for example in [10], while specific topics are tackled in several works: flow control protocols [11], router power estimations [12], Quality of Service (QoS) provisions [13], [14], asynchronous implementations [15], [16], [17]. CAD tools for NoC instantiation and optimization can be found for example in [18], [19].…”

Section: B Network-on-chipmentioning

confidence: 99%

Supporting vertical links for 3D networks-on-chip: toward an automated design and analysis flow

Loi

Angiolini

Benini

2007

Proceedings of the Second International Conference on Nano-Networks

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Abstract-Three-dimensional (3D) manufacturing technologies are viewed as promising solutions to the bandwidth bottlenecks in VLSI communication. At the architectural level, Networkson-chip (NoCs) have been proposed to address the complexity of interconnecting an ever-growing number of cores, memories and peripherals. NoCs are a promising choice for implementing scalable 3D interconnect architectures. However, the development of 3D NoCs is still at an early development stage. In this paper, we present a semi-automated design flow for 3D NoCs. Starting from an accurate physical and geometric model of ThroughSilicon Vias (TSVs), we extract a circuit-level model for vertical interconnections, and we use it to evaluate the design implications of extending switch architectures with ports in the vertical direction. In addition, we present a design flow allowing for post-layout simulation of NoCs with links in all three physical dimensions.

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“…While techniques such as link pipelining have been proposed to overcome link latency [64,70], the cycle-level synchronicity severely constrains the clock distribution [78] and negatively affects the scalability [12]. A range of asynchronous networks [3,10,66] completely remove the need for a clock, and aim to leverage the characteristics of asynchronous circuits to reduce power and electromagnetic emissions. While offering physical scalability, these networks rely on not yet well-established design methodologies and verification techniques.…”

Section: Physical Scalabilitymentioning

confidence: 99%

A quantitative evaluation of a Network on Chip design flow for multi-core consumer multimedia applications

Hansson

Goossens

2011

Des Autom Embed Syst

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A growing number of applications are integrated on the same System on Chip in the form of hardware and software Intellectual Property (IP). Many applications have firm or soft real-time requirements and require bounds on latency and throughput. To accommodate the growing number of application requirements, the on-chip interconnect must offer scalability on the physical, architectural and functional level.Networks on Chip (NoC) are proposed as a scalable communication architecture that is also able to deliver guaranteed performance. Traditionally, NoCs focus on delivering physical and architectural scalability. The functional scalability, i.e. the ability to satisfy an increasing number of increasingly demanding requirements with a constant cost/performance ratio, is often overlooked. The onus is on the interconnect design flow that translates user requirements to an interconnect instance. While mature tooling exists for many of the IPs, interconnect design flows are an active research area, with few concrete examples, and few large-scale case studies.As the main contribution of this work, we demonstrate a complete operational interconnect design flow for multiple real-time applications, and quantitatively evaluate the functional scalability on two large-scale industrial case studies. We illustrate the steps of the flow, going from requirement specification all the way to simulation of synthesised netlists in a 90 nm and 65 nm low-power standard-cell technology. We show that the interconnect and design flow offer scalability, on the physical, architectural as well as the functional level.

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A Scheduling Discipline for Latency and Bandwidth Guarantees in Asynchronous Network-on-Chip

Abstract: Guaranteed services (GS)

Cited by 80 publications

References 18 publications

Realization of Efficient High Throughput Buffering Policies for Network on Chip Router

Realization of Efficient High Throughput Buffering Policies for Network on Chip Router

Supporting vertical links for 3D networks-on-chip: toward an automated design and analysis flow

A quantitative evaluation of a Network on Chip design flow for multi-core consumer multimedia applications

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