A scanisland based design enabling prebond testability in die-stacked microprocessors

Lewis, Dean L.; Lee, H.-H.S.

doi:10.1109/test.2007.4437621

Cited by 75 publications

(35 citation statements)

References 28 publications

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“…Early papers addressing the testability issues of 3D-SICs are by Lewis and Lee [17,18]. They focus on pre-bond die testing to increase the compound stack yield and propose a "scan island" approach, which is essentially the wrapper technique from IEEE Stds 1149.1 [9,28] and 1500 [5,11] under a different name.…”

Section: Related Prior Workmentioning

confidence: 99%

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A DfT Architecture for 3D-SICs Based on a Standardizable Die Wrapper

et al. 2011

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Process technology developments enable the creation of three-dimensional stacked ICs (3D-SICs) interconnected by means of Through-Silicon Vias (TSVs). This paper presents a 3D Design-for-Test (DfT) architecture for such 3D-SICs that allows prebond die testing as well as mid-bond and post-bond stack testing. The architecture enables a modular test approach, in which the various dies, their embedded IP cores, the inter-die TSV-based interconnects, and the external I/Os can be tested as separate units, which allows flexible optimization of the 3D-SIC test flow and provides yield monitoring and first-order fault diagnosis. The architecture builds on and reuses existing DfT hardware at the core, die, and product level.

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Section: Related Prior Workmentioning

confidence: 99%

“…As long as that is the case, it is a requirement to provide dedicated probe pads for pre-bond wafer test access [14,17,23] for all dies in the stack, apart from the bottom die.…”

Section: Assumptions and Requirementsmentioning

confidence: 99%

A DfT Architecture for 3D-SICs Based on a Standardizable Die Wrapper

et al. 2011

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“…Integrated circuits (ICs) with multiple chips (dies) stacked and bonded vertically, interconnected with Through-Silicon Vias (TSVs), so called 3D TSV Stacked ICs (TSV-SICs), have lately attracted a fair amount of research [7][8][9][10]18]. Recent research have addressed test architecture design for 3D TSV-SICs [15], testing the TSVs [7-10, 15, 18] and 3D TSV-SIC specific defects [7,10].…”

Section: Introductionmentioning

confidence: 99%

Scheduling Tests for 3D Stacked Chips under Power Constraints

2011

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This paper addresses Test Application Time (T AT) reduction under power constraints for corebased 3D Stacked ICs (SICs) connected by Through Silicon Vias (TSVs). Unlike non-stacked chips, where the test flow is well defined by applying the same test schedule both at wafer sort and at package test, the test flow for 3D TSV-SICs is yet undefined. In this paper we present a cost model to find the optimal test flow. For the optimal test flow, we propose test scheduling algorithms that take the particulars of 3D TSV-SICs into account. A key challenge in testing 3D TSV-SICs is to reduce the T AT by co-optimizing the wafer sort and the package test while meeting power constraints. We consider a system of chips with cores that are accessed through an on-chip JTAG infrastructure and propose a test scheduling approach to reduce T AT while considering resource conflicts and meeting the power constraints. Depending on the test schedule, the JTAG interconnect lines that are required can be shared to test several cores. This is taken into account in experiments with an implementation of the proposed scheduling approach. The results show significant savings in T AT.

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“…Integrated circuits (ICs) with multiple chips (dies), so called 3D Stacked ICs (SICs), have recently attracted a fair amount of research [1][2][3][4][5]. A 3D-SIC is obtained by stacking and bonding individual chips, which are connected by Through-Silicon Vias (TSVs).…”

Section: Introductionmentioning

confidence: 99%

“…Due to imperfections in IC manufacturing, each individual chip must be tested. Recent research has addressed test architecture design for 3D-SICs [6], testing the TSVs [1][2][3][4][5][6] and 3D-SIC-specific defects [1,2]. Testing each individual chip is required for both 3D-SICs and traditional non-stacked ICs.…”

Section: Introductionmentioning

confidence: 99%

Scheduling Tests for 3D Stacked Chips under Power Constraints

Gupta¹,

Ingelsson²,

Larsson³

2011

2011 Sixth IEEE International Symposium on Electronic Design, Test and Application

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Abstract-This paper addresses Test Application Time (TAT) reduction for core-based 3D Stacked ICs (SICs). Applying traditional test scheduling methods used for non-stacked chip testing where the same test schedule is applied both at wafer test and at final test to SICs, leads to unnecessarily high TAT. This is because the final test of 3D-SICs includes the testing of all the stacked chips. A key challenge in 3D-SIC testing is to reduce TAT by co-optimizing the wafer test and the final test while meeting power constraints. We consider a system of chips with cores equipped with dedicated Built-In-Self-Test (BIST)-engines and propose a test scheduling approach to reduce TAT while meeting the power constraints. Depending on the test schedule, the control lines that are required for BIST can be shared among several BIST engines. This is taken into account in the test scheduling approach and experiments show significant savings in TAT.

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A scanisland based design enabling prebond testability in die-stacked microprocessors

Cited by 75 publications

References 28 publications

A DfT Architecture for 3D-SICs Based on a Standardizable Die Wrapper

A DfT Architecture for 3D-SICs Based on a Standardizable Die Wrapper

Scheduling Tests for 3D Stacked Chips under Power Constraints

Scheduling Tests for 3D Stacked Chips under Power Constraints

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