A scalable load balancer for forwarding internet traffic

Shi, Weiguang; MacGregor, M.H.; Gburzyński, Paweł

doi:10.1145/1095890.1095911

Cited by 16 publications

(14 citation statements)

References 16 publications

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“…Although both tasks are hard due to deeper packet content to inspect and more complicated states to maintain, they can be implemented as degenerated or simplified versions [26] [27]. Our future work also includes the implementation of flow-level load balancing [31][32][33] and application-level flow detection [35][36][37] on the IXP2850 NP.…”

Section: Resultsmentioning

confidence: 99%

“…Note that W. Shi, M. H. MacGregor and P. Gburzynski have proved that pure hashing is not able to well balance the workload due to the Zipf-like distributions of flow-size in real-life traffic [32]. However, in practice, the performance of hash-based load balancing module is good enough (see the experiments in Section 6.4.1)…”

Section: Workload Allocation By Crc Hashingmentioning

confidence: 99%

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Towards high-performance flow-level packet processing on multi-core network processors

et al. 2007

Proceedings of the 3rd ACM/IEEE Symposium on Architecture for Networking and Communications Systems

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There is a growing interest in designing high-performance network devices to perform packet processing at flow level. Applications such as stateful access control, deep inspection and flow-based load balancing all require efficient flow-level packet processing. In this paper, we present a design of high-performance flow-level packet processing system based on multi-core network processors. Main contribution of this paper includes: a) A high performance flow classification algorithm optimized for network processors; b) An efficient flow state management scheme leveraging memory hierarchy to support large number of concurrent flows; c) Two hardware-optimized order-preserving strategies that preserve internal and external per-flow packet order. Experimental results show that: a) The proposed flow classification algorithm, AggreCuts, outperforms the well-known HiCuts algorithm in terms of classification rate and memory usage; b) The presented SigHash scheme can manage over 10M concurrent flow states on the Intel IXP2850 NP with extremely low collision rate; c) The performance of internal packet order-preserving scheme using SRAM queue-array is about 70% of that of external packet orderpreserving scheme realized by ordered-thread execution.

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Section: Resultsmentioning

confidence: 99%

Section: Workload Allocation By Crc Hashingmentioning

confidence: 99%

Towards high-performance flow-level packet processing on multi-core network processors

et al. 2007

Proceedings of the 3rd ACM/IEEE Symposium on Architecture for Networking and Communications Systems

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“…The purpose of DTP is to spread out the tasks of different flows across the entire network. This helps to avoid the overstress on a small portion of the network, and to further improve the efficiency and reliability of the entire multi-core system [7] [8]. The basic idea of tile partitioning is to organize all the cores into several necessary partitions.…”

Section: A Dynamic Tile Partitioningmentioning

confidence: 99%

NBTI aware workload balancing in multi-core systems

Sun

Kodi

Louri

et al. 2009

2009 10th International Symposium on Quality of Electronic Design

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Abstract-As device feature size continues to shrink, reliability becomes a severe issue due to process variation, particle-induced transient errors, and transistor wear-out/stress such as Negative Bias Temperature Instability (NBTI). Unless this problem is addressed, chip multi-processor (CMP) systems face low yields and short mean-time-to-failure (MTTF). This paper proposes a new design framework for multi-core system that includes device wear-out impact. Based on device fractional NBTI model, we propose a new NBTI aware system workload model, and develop new dynamic tile partition (DTP) algorithm to balance workload among active cores while relaxing stressed ones. Experimental results on 64 cores show that by allowing a small number of cores (around 10%)to relax in a short time period (10 second), the proposed methodology improves CMP system yield. We use the percentage of core failure to represent the yield improvement. The new strategy improves the core failure number by 20 %, and extend MTTF by 30% with little degradation in performance (less than 6%).

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“…Traffic balancing is a difficult problem for parallel IP lookup engines [26]. Many solutions have been proposed, including learning-based block rearrangedment [16], [17] and IP / prefix caching [18], [19].…”

Section: Parallel Ip Lookup Enginesmentioning

confidence: 99%

Beyond TCAMs: An SRAM-Based Parallel Multi-Pipeline Architecture for Terabit IP Lookup

Jiang

Wang

Prasanna

2008

IEEE INFOCOM 2008 - The 27th Conference on Computer Communications

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Abstract-Continuous growth in network link rates poses a strong demand on high speed IP lookup engines. While Ternary Content Addressable Memory (TCAM) based solutions serve most of today's high-end routers, they do not scale well for the next-generation [1]. On the other hand, pipelined SRAMbased algorithmic solutions become attractive. Intuitively multiple pipelines can be utilized in parallel to have a multiplicative effect on the throughput. However, several challenges must be addressed for such solutions to realize high throughput. First, the memory distribution across different stages of each pipeline as well as across different pipelines must be balanced. Second, the traffic on various pipelines should be balanced.In this paper, we propose a parallel SRAM-based multipipeline architecture for terabit IP lookup. To balance the memory requirement over the stages, a two-level mapping scheme is presented. By trie partitioning and subtrie-to-pipeline mapping, we ensure that each pipeline contains approximately equal number of trie nodes. Then, within each pipeline, a fine-grained node-to-stage mapping is used to achieve evenly distributed memory across the stages. To balance the traffic on different pipelines, both pipelined prefix caching and dynamic subtrie-topipeline remapping are employed. Simulation using real-life data shows that the proposed architecture with 8 pipelines can store a core routing table with over 200K unique routing prefixes using 3.5 MB of memory. It achieves a throughput of up to 3.2 billion packets per second, i.e. 1 Tbps for minimum size (40 bytes) packets.

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A scalable load balancer for forwarding internet traffic

Cited by 16 publications

References 16 publications

Towards high-performance flow-level packet processing on multi-core network processors

Towards high-performance flow-level packet processing on multi-core network processors

NBTI aware workload balancing in multi-core systems

Beyond TCAMs: An SRAM-Based Parallel Multi-Pipeline Architecture for Terabit IP Lookup

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