A scalable high-frequency noise model for bipolar transistors with application to optimal transistor sizing for low-noise amplifier design

Abstract

Fully scalable, analytical HF noise parameter equations for bipolar transistors are presented and experimentally tested on high-speed Si and SiGe technologies. A technique for extracting the complete set of transistor noise parameters from Y parameter measurements only is developed and verified. Finally, the noise equations are coupled with scalable variants of the HICUM and SPICE-Gummel-Poon models and are employed in the design of tuned low noise amplifiers (LNA's) in the 1.9-, 2.4-, and 5.8-GHz bands.

A novel frequency independent third-order intermodulation distortion cancellation technique for BJT amplifiers

“…For the analysis, we assume that . Thus, the basic nonlinearities can be described as a Taylor series expansion up to the third degree, as follows: (2) where the Taylor coefficients are (3) Furthermore, we assume the base-emitter depletion capacitance and the collector-base depletion capacitance to be linear. This is justified as long as the transistor is operated at a relatively low .…”

A method to simultaneously extract the small‐signal equivalent circuit and noise parameters of heterojunction bipolar transistors

“…These figures for L are selected according to the frequency dependence of the power spectral densities observed in (18). Then, substituting (26) into (23), an equation system with eight unknowns (polynomial coefficients C ij l ) is obtained.…”

“…Several works in the literature propose models to compute the NPs of an HBT from the admittance parameters, [17][18][19], but those models only describe the intrinsic-device noise behavior. Additionally, the method in [18] requires previous knowledge of the values of the base and emitter resistances. Therefore, to use those models for obtaining the NPs, the parasitic elements must be extracted first from S-parameter or Y-parameter measurements, through a de-embedding procedure.…”

Integrated Phased Array Systems in Silicon

“…The input transistor size and dc current are chosen to obtain power and noise matching simultaneously by following the steps described in [26]. After the current density associated with minimum noise figure is determined from simulations, the input transistor is scaled until the optimum input impedance for low noise has a 50-real part.…”